R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 927

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6)
The plane n mode registers (PnMR, n = 1 to 6) set the display operation for plane n.
Internal update:
Internal update:
Bit
31 to 21 ⎯
20
19, 18
17
16
15
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
PnYCDF
⎯
PnTC
PnWAE
⎯
31
15
—
—
R
R
0
0
R/W
30
14
—
O
R
0
0
0
Initial
Value
All 0
0
All 0
0
0
PnSPIM
R/W
29
—
13
R
O
0
0
R/W
28
12
—
R
O
0
0
R/W
R
R/W
R
R/W
R/W
R
27
11
—
—
R
R
0
0
Internal
Update
⎯
Yes
⎯
Yes
Yes
⎯
26
10
—
—
R
R
0
0
R/W
25
—
O
R
0
9
0
PnCPSL
Plane n Wrap Around Enable
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Plane n YC Data Format
0: Sets the order of YC data to UYVY format.
1: Sets the order of YC data to YUYV format.
Reserved
These bits are always read as 0. The write value
should always be 0.
Plane n Transparent Color
0: When set to 8 bits/pixel display, the
1: When set to 8 bits/pixel display, any of the
0: Wraparound is not performed for plane n
1: Wraparound is performed for plane n
Reserved
This bit is always read as 0. The write value
should always be 0.
R/W
24
—
R
O
0
8
0
transparent color is the color set in the plane
n transparent color 1 register (PnTC1R)
transparent colors set in CP1TR to CP4TR
can be a transparent color
CP1TR to CP4TR to be used are determined
by the setting of the PnCPSL bit.
PnDC
R/W
23
—
R
O
0
7
0
Rev.1.00 Jan. 10, 2008 Page 895 of 1658
22
—
—
R
R
0
6
0
R/W
21
—
O
R
0
5
0
PnBM
PnYCDF
R/W
R/W
20
O
O
0
4
0
19. Display Unit (DU)
19
—
—
R
R
0
3
0
REJ09B0261-0100
18
—
—
R
R
0
2
0
PnTC
R/W
R/W
17
O
O
0
1
0
PnDDF
PnWAE
R/W
R/W
16
O
O
0
0
0