R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1213

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the data transmission should be
temporarily halted by FIFO full/empty, and it should be resumed when the preparation has been
completed.
In multiple block transfer, the transfer should be temporarily halted at every block break to select
either to continue to the next block or to abort the multiple block transfer command by issuing the
CMD12 command. To continue to the next block, the RD_CONTI and DATAEN bits should be
set to 1. To issue the CMD12 command, the CMDOFF bit should be set to 1 to abort the command
sequence on the MMCIF side. When using the auto-mode for a pre-defined multiple block
transfer, the setting of the RD_CONTI bit or the DATAEN bit between blocks can be omitted.
24.3.4
CSTR indicates the MMCIF status during command sequence execution.
Bit
7
6
Card Status Register (CSTR)
Bit Name
BUSY
FIFO_FULL 0
Initial value:
Initial
Value
0
R/W:
Bit:
BUSY
7
0
R
R/W
R
R
FIFO_
FULL
R
6
0
Description
Command Busy
Indicates command execution status. When the
CMDOFF bit in OPCR is set to 1, this bit is cleared to 0
because the MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state
1: Command sequence execution in progress
FIFO Full
This bit is set to 1 when the FIFO becomes full while
data is being received from the card, and cleared to 0
when RD_CONTI is set to 1 or the command sequence
is completed.
Indicates whether the FIFO is empty or not.
0: The FIFO is empty.
1: The FIFO is full.
EMPTY
FIFO_
R
5
0
CWRE
4
0
R
DTBUSY
R
3
0
Rev.1.00 Jan. 10, 2008 Page 1181 of 1658
DTBUSY
_TU
—
2
R
24. Multimedia Card Interface (MMCIF)
—
R
1
0
REQ
R
0
0
REJ09B0261-0100