R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 268

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8. Caches
8.6.4
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed are specified in the address field, and
the longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the way is
specified by bits [14:13] and the entry by bits [12:5]. Address field bits [4:2] are used for the
longword data specification in the entry. As only longword access is used, 0 should be specified
for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
1. OC data array read
2. OC data array write
Rev.1.00 Jan. 10, 2008 Page 236 of 1658
REJ09B0261-0100
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the way and entry set in the address
field.
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding to the way and entry set in
the address field. This write does not set the U bit to 1 on the address array side.
Figure 8.7 Memory-Mapped OC Address Array (Cache size = 32 Kbytes)
OC Data Array
Address field
Data field
31
31
U
1 1 1 1 0 1 0 0
V
A
*
: Validity bit
: Dirty bit
: Association bit
: Reserved bits (write value should be 0 and read value is undefined )
: Don't care
24
23
* * * * * * * * *
Tag
15
Way
14
1312
10 9
Entry
5 4 3 2 1 0
0
A
0
2
U
0 0
1 0
V