R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1197

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23.4
23.4.1
Figure 23.2 shows the flow of a transmit/receive operation procedure.
Depending on the settings of SPCR, the master transmits data to the slave on either the falling or
rising edge of HSPI_CLK and samples data from the slave at the opposite edge. The data transfer
between the master and slave is completed when the transmit complete status flag (TXFN) in
SPSR is set to 1. This flag should be used to identify when an HSPI transfer event (byte
transmitted and byte received) has occurred, even in the case where the HSPI module is used to
receive data only (null data being transmitted). By default data is transmitted MSB first, but LSB
first is also possible depending on how the LMSB bit in SPSCR is set.
During the transmit operation the slave responds by sending data to the master synchronized with
the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the
shift register in the module and on completion of the transmit operation, is transferred to SPRBR.
Operation
Operation Overview with FIFO Mode Disabled
Yes
operation by setting the MASL bit
setting TFIE and ROIE bits in
Select required interrupts by
Select master or slave
Write data to SPTBR
reading the TXFL bit
SPTBR is empty by
transmit required?
Reset the system
Figure 23.2 Operational Flowchart
in SPSCR
in SPSR
Check if
SPSCR
Another
Start
End
No
Yes
No
Rev.1.00 Jan. 10, 2008 Page 1165 of 1658
TX/RX data to/from slave
23. Serial Peripheral Interface (HSPI)
REJ09B0261-0100