R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 259

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.4
8.4.1
When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable
area, the instruction cache operates as follows:
1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual
2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting
3. Cache hit
4. Cache miss
8.4.2
When the IC is enabled (ICE = 1 in CCR) and instruction prefetches are performed from a
cacheable area, the instruction cache operates as follows:
1. The tag, V bit, Ubit and LRU bits on each way are read from the cache line indexed by virtual
2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting
address bits [12:5].
from virtual address translation by the MMU:
⎯ If there is a way whose tag matches and the V bit is 1, see No. 3.
⎯ If there is no way whose tag matches and the V bit is 1, see No. 4.
The data indexed by virtual address bits [4:2] is read as an instruction from the data field on
the hit way. The LRU bits are updated to indicate the way is the latest one.
Data is read into the cache line on the way which selected using LRU bits to replace from the
physical address space corresponding to the virtual address. Data reading is performed, using
the wraparound method, in order from the quad-word data (8 bytes) including the cache-
missed data, and when the corresponding data arrives in the cache, the read data is returned to
the CPU as an instruction. While the remaining one cache line of data is being read, the CPU
can execute the next processing. When reading of one line of data is completed, the tag
corresponding to the physical address is recorded in the cache, and 1 is written to the V bit, the
LRU bits are updated to indicate the way is the latest one.
address bits [12:5].
from virtual address translation by the MMU:
⎯ If there is a way whose tag matches and the V bit is 1, see No. 3.
⎯ If there is no way whose tag matches and the V bit is 1, see No. 4.
Instruction Cache Operation
Read Operation
Prefetch Operation
Rev.1.00 Jan. 10, 2008 Page 227 of 1658
REJ09B0261-0100
8. Caches