R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 17

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR2-SDRAM Interface (DBSC2)
12.1 Features.............................................................................................................................. 457
12.2 Input/Output Pins ............................................................................................................... 460
12.3 Data Alignment.................................................................................................................. 465
12.4 Register Descriptions ......................................................................................................... 479
12.5 DBSC2 Operation .............................................................................................................. 512
11.5.9
11.5.10 Master Mode....................................................................................................... 450
11.5.11 Slave Mode ......................................................................................................... 451
11.5.12 Cooperation between Master and Slave.............................................................. 451
11.5.13 Power-Down Mode and Bus Arbitration ............................................................ 451
11.5.14 Mode Pin Settings and General Input Output Port Settings about
11.5.15 Pins Multiplexed with Other Modules Functions ............................................... 452
11.5.16 Register Settings for Divided-Up DACKn Output ............................................. 452
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
12.4.7
12.4.8
12.4.9
12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) .......................................... 502
12.4.11 SDRAM Refresh Status Register (DBRFSTS) ................................................... 504
12.4.12 DDRPAD Frequency Setting Register (DBFREQ) ............................................ 505
12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)..................... 507
12.4.14 SDRAM Mode Setting Register (DBMRCNT) .................................................. 510
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.5.6
12.5.7
12.5.8
12.5.9
12.5.10 DDR2-SDRAM Power Supply Backup Function............................................... 546
Bus Arbitration ................................................................................................... 448
Data Bus Width................................................................................................... 452
DBSC2 Status Register (DBSTATE) ................................................................. 482
SDRAM Operation Enable Register (DBEN)..................................................... 483
SDRAM Command Control Register (DBCMDCNT) ....................................... 484
SDRAM Configuration Setting Register (DBCONF)......................................... 486
SDRAM Timing Register 0 (DBTR0) ................................................................ 488
SDRAM Timing Register 1 (DBTR1) ................................................................ 492
SDRAM Timing Register 2 (DBTR2) ................................................................ 495
SDRAM Refresh Control Register 0 (DBRFCNT0) .......................................... 499
SDRAM Refresh Control Register 1 (DBRFCNT1) .......................................... 500
Supported SDRAM Commands.......................................................................... 512
SDRAM Command Issue ................................................................................... 513
Initialization Sequence........................................................................................ 516
Self-Refresh Operation ....................................................................................... 517
Auto-Refresh Operation...................................................................................... 520
Regarding Address Multiplexing........................................................................ 521
Regarding SDRAM Access and Timing Constraints.......................................... 530
Important Information Regarding Use of 8-Bank DDR2-SDRAM Products ..... 544
Important Information Regarding ODT Control Signal Output to SDRAM ...... 544
.......................................................... 457
Rev.1.00 Jan. 10, 2008 Page xv of xxx
REJ09B0261-0100