R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1529

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Number
371
370
369
368
367
366
365
364
363
362
361
360
359
358
357
356
355
354
353
352
351
350
349
348
347
346
345
344
343
342
341
Pin Name
D46/AD14/DB2
D46/AD14/DB2
D45/AD13/DB1
D45/AD13/DB1
D45/AD13/DB1
D44/AD12/DB0
D44/AD12/DB0
D44/AD12/DB0
D43/AD11/DG5
D43/AD11/DG5
D43/AD11/DG5
D42/AD10/DG4
D42/AD10/DG4
D42/AD10/DG4
D41/AD9/DG3
D41/AD9/DG3
D41/AD9/DG3
D40/AD8/DG2
D40/AD8/DG2
D40/AD8/DG2
D39/AD7/DG1
D39/AD7/DG1
D39/AD7/DG1
D38/AD6/DG0
D38/AD6/DG0
D38/AD6/DG0
D37/AD5/DR5
D37/AD5/DR5
D37/AD5/DR5
D36/AD4/DR4
D36/AD4/DR4
Type
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Number
340
339
338
337
336
335
334
333
332
331
330
329
328
327
326
325
324
323
322
321
320
319
318
317
316
315
314
313
312
311
310
Rev.1.00 Jan. 10, 2008 Page 1497 of 1658
Pin Name
30. User Debugging Interface (H-UDI)
D36/AD4/DR4
D35/AD3/DR3
D35/AD3/DR3
D35/AD3/DR3
D34/AD2/DR2
D34/AD2/DR2
D34/AD2/DR2
D33/AD1/DR1
D33/AD1/DR1
D33/AD1/DR1
D32/AD0/DR0
D32/AD0/DR0
D32/AD0/DR0
CLKOUTENB
CLKOUTENB
CLKOUTENB
CLKOUT
CLKOUT
CLKOUT
RDY
RDY
RDY
WE3
WE3
WE3
WE2
WE2
WE2
WE1
WE1
WE1
REJ09B0261-0100
Type
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output
Input
Control
Output