R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1063

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20.7
When using the GDTA, note the following:
20.7.1
During GDTA operation, the CPG register settings must not be done to stop a module (other
modules as well as the GDTA). If a module is stopped during GDTA operation, the GDTA
processing is stopped and processing contents set in CL/MC command FIFO are cleared.
When stopping the module, settings should be changed to stop the module only after confirming
that the CLSR.EXE bit (bit 3) in CLSR is 0 and the MC_CFA bits (bits 10 to 8) in MCSR are 000.
In order to resume the processing, the procedure described in section 20.4.1 (3), CL Processing
Procedure or section 20.4.2 (2), MC Processing Procedure should be used after releasing the
module stop. (After a module is stopped, the processing that was in progress and processing
contents set in the CL/MC command FIFO should be performed again.)
20.7.2
During GDTA operation, deep sleep mode must not be entered. If a transition is made to deep
sleep mode during GDTA operation, the GDTA processing is stopped and processing contents set
in CL/MC command FIFO are cleared.
When entering deep sleep mode, a transition should be made only after confirming that the
CLSR.EXE bit (bit 3) in CLSR is 0, and also after confirming that the MC_CFA bits (bits 10 to 8)
in MCSR are 000.
In order to resume the processing, the procedure described in section 20.4.1 (3), CL Processing
Procedure or section 20.4.2 (2), MC Processing Procedure should be used after releasing the deep
sleep mode. (After deep sleep mode is entered, the processing that was in progress and processing
contents set in the CL/MC command FIFO should be performed again.)
Usage Notes
Regarding Module Stoppage
Regarding Deep Sleep Modes
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 1031 of 1658
REJ09B0261-0100