R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 520

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12. DDR2-SDRAM Interface (DBSC2)
12.4.5
The SDRAM timing register 0 (DBTR0) is a readable/writable register. It is initialized only upon
power-on reset.
Rev.1.00 Jan. 10, 2008 Page 488 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 27 ⎯
26 to 24 CL2 to CL0 010
R/W:
R/W:
BIt:
BIt:
SDRAM Timing Register 0 (DBTR0)
Bit Name
31
15
⎯
⎯
R
R
0
0
TRFC6
R/W
30
⎯
14
R
0
0
TRFC5
R/W
29
⎯
13
Initial
Value
All 0
R
0
0
TRFC4
R/W
28
12
⎯
R
0
0
TRFC3
R/W
27
11
⎯
R
0
0
R/W
R
R/W
TRFC2
R/W
R/W
CL2
26
10
0
1
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
CAS Latency Setting Bits
These bits set the CAS latency. These bits should be
set according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
When using the ODT (On Die Termination) enable
output signal MODT, these bits should be set to 4 or
more cycles.
000: Setting prohibit (If specified, correct operation
001: Setting prohibit (If specified, correct operation
010: 2 cycles
011: 3 cycles
100: 4 cycles
101: 5 cycles
110: 6 cycles
111: Setting prohibit (If specified, correct operation
TRFC1
R/W
R/W
CL1
25
1
9
0
cannot be guaranteed.)
cannot be guaranteed.)
cannot be guaranteed.)
TRFC0
R/W
R/W
CL0
24
0
8
1
23
⎯
⎯
R
R
0
7
0
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
TRAS3
R/W
19
⎯
R
0
3
0
TRCD2
TRAS2
R/W
R/W
18
0
2
0
TRCD1
TRAS1
R/W
R/W
17
1
1
0
TRCD0
TRAS0
R/W
R/W
16
1
0
1