R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1248

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24. Multimedia Card Interface (MMCIF)
(5)
Flash memory operation commands include a number of commands involving read data. Such
commands confirm the card status by the command argument and command response, and receive
card information and flash memory data from the MMCDAT pin.
In multiple block transfer, two transfer methods can be used; one is open-ended and another one is
pre-defined. Open-ended operation is suspended for each block transfer and an instruction to
continue or end the command sequence is waited for. For pre-defined operation, the block number
of the transmission is set before transfer.
When the FIFO is full between blocks in multiple block transfer, the command sequence is
suspended. Once the command sequence is suspended, process the data in FIFO if necessary
before allowing the command sequence to continue.
Note: In multiple block transfer, when the command sequence is ended (the CMDOFF bit is
Figures 24.8 to 24.11 show examples of the command sequence for commands with read data.
Figures 24.12 to 24.14 show the operational flows for commands with read data.
• Make settings to issue the command, and clear FIFO.
• Set the CMDSTART bit in CMDSTRT to 1 to start command transmission. MMCCMD must
• The command response is received from the card.
• Read data is received from the card.
• The inter-block suspension in multiple block transfer and suspension by the FIFO full are
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be kept driven until the end bit output is completed.
Command transmission completion can be confirmed by the command transmit end interrupt
(CMDI).
If the card does not return the command response, the command response is detected by the
command timeout error (CTERI).
detected by the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively.
To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To end
the command sequence, the CMDOFF bit in OPCR should be set to 1, and CMD12 should be
issued. Unless the sequence is suspended in pre-defined multiple block transfer, CMD12 is not
needed.
Commands with Read Data
written to 1) before command response reception (CRPI), the command response may not
be received correctly. Therefore, to receive the command response correctly, the command
sequence must be continued (set the RD_CONT bit to 1) until the command response
reception ends.