IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet

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... PCI Express Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-PCI10605-2.8 PCI Express Compiler User Guide ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... PCI Express Reconfiguration Block Interface (Hard IP Only 4–7 MSI (Message Signal Interrupt) Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Avalon-MM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Transmit Virtual Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 December 2010 Altera Corporation Contents PCI Express Compiler User Guide ...

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... Non-bursting Avalon-MM CRA Slave Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–50 RX Avalon-MM Master Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–51 64-Bit Bursting TX Avalon-MM Slave Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–51 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–52 Reset and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–53 Physical Layer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–54 Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–54 Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–56 PCI Express Compiler User Guide Contents December 2010 Altera Corporation ...

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... Active State Power Management (ASPM 9–3 Exit Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Acceptable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Lane Initialization and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 Instantiating Multiple PCI Express IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6 Clock and Signal Requirements for Devices with Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6 Source Multiple Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7 December 2010 Altera Corporation v PCI Express Compiler User Guide ...

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... Configuration Space Bus and Device Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–28 Configuration of Root Port and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–28 Issuing Read and Write Transactions to the Application Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–33 BFM Procedures and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–34 BFM Read and Write Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–34 ebfm_barwr Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–35 PCI Express Compiler User Guide Contents December 2010 Altera Corporation ...

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... Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–51 dma_wr_test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 dma_set_rd_desc_data Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 dma_set_wr_desc_data Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 dma_set_header Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 rc_mempoll Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–53 msi_poll Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–53 dma_set_msi Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–54 find_mem_bar Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–54 dma_set_rclast Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–55 ebfm_display_verb Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–55 December 2010 Altera Corporation vii PCI Express Compiler User Guide ...

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... Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2 Stratix II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2 Stratix III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3 Stratix IV Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3 Avalon-MM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3 Arria GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–4 Cyclone III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–4 Stratix II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–5 Stratix III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–5 PCI Express Compiler User Guide Contents December 2010 Altera Corporation ...

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... Arria GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–7 Cyclone III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–7 Stratix II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–8 Stratix III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–8 Stratix IV Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–9 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–8 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–8 December 2010 Altera Corporation ix PCI Express Compiler User Guide ...

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... PCI Express Compiler User Guide Contents December 2010 Altera Corporation ...

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... December 2010 <edit Part Number variable in chapter> This document describes Altera’s IP core for PCI Express. PCI Express is a high-performance interconnect protocol for use in a variety of applications including network adapters, storage area networks, embedded controllers, graphic accelerator boards, and audio-video products. The PCI Express protocol is software backwards-compatible with the earlier PCI and PCI-X protocols, but is significantly different from its predecessors ...

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... Avalon-ST interface and the following capabilities: Gen1 ×1, ×4 64-bit interface, Gen1 ×8 128-bit interface. ■ Gen2 ×1, 64-bit interface, Gen2 ×4, 128-bit interface. ■ Single virtual channel. ■ PCI Express Compiler User Guide Chapter 1: Datasheet Features December 2010 Altera Corporation ...

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... Number of virtual channels Reordering of out–of–order completions (transparent to the application layer) Requests that cross 4 KByte address boundary (transparent to the application layer) December 2010 Altera Corporation Table 1–2 outlines these different features. Hard IP Implementation MegaWizard Plug- SOPC Builder In Manager Desing Design Flow ...

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... IP core. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and IP core versions older than one release. Device Family Support IP cores provide either full or preliminary support for target Altera device families: PCI Express Compiler User Guide Hard IP Implementation MegaWizard Plug- ...

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... The PCI Express Compiler generates customized PCI Express IP cores you use to design PCI Express root ports or endpoints, including non-transparent bridges, or truly unique designs combining multiple PCI Express components in a single Altera device. The PCI Express IP cores implement all required and most optional features of the PCI Express specification for the transaction, data link, and physical layers ...

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... PCI Express TL Protocol Stack Interface Virtual Channel Retry Buffer RX Buffer PCI Express Reconfiguration 2.0. Chapter 1: Datasheet General Description Figure 1–1 FPGA Fabric Adapter Application Note (3) Layer LMI Test, Debug & PCIe Configuration Reconfig Logic and PCI Express Base December 2010 Altera Corporation ...

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... It reduces system costs by reducing the size of the flash device to store the .pof. ■ It facilitates hardware acceleration. It may reduce system size because a single CvPCIe link can be used to configure ■ multiple FPGAs. December 2010 Altera Corporation programmed. After the PCI Express link is established, it can be Host CPU Download cable Serial or ...

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... Data link ■ Transaction Optimized for Altera devices, the hard IP implementation supports all memory, I/O, configuration, and message transactions. The IP cores have a highly optimized application interface to achieve maximum effective throughput. Because the compiler is parameterizeable, you can customize the IP cores to meet your design requirements.Table 1– ...

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... You can use the MegaWizard Plug-In Manager or SOPC Builder to customize the IP core. two PCI Express IP cores, one configured as a root port and the other as an endpoint. Figure 1–3. PCI Express Application with a Single Root Port and Endpoint Altera FPGA with Embedded PCIe Hard IP Block User Application Logic December 2010 Altera Corporation × ...

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... Note to Figure 1–4: (1) Altera does not recommend Stratix family devices for new designs. If you target a device that includes an internal transceiver, you can parameterize the PCI Express IP core to include a complete PHY layer, including the MAC, PCS, and PMA layers. If you target other device architectures, the PCI Express Compiler generates the IP core with the Intel-designed PIPE interface, making the IP core usable with other PIPE-compliant external PHY devices ...

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... External PHY Support Altera PCI Express IP cores support a wide range of PHYs, including the TI XIO1100 PHY in 8-bit DDR/SDR mode or 16-bit SDR mode; NXP PX1011A for 8-bit SDR mode, a serial PHY, and a range of custom PHYs using 8-bit/16-bit SDR with or without source synchronous transmit clock modes and 8-bit DDR with or without source synchronous transmit clock modes ...

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... Random tests that test a wide range of traffic patterns across one or more virtual channels Compatibility Testing Environment Altera has performed significant hardware testing of the PCI Express IP cores to ensure a reliable solution. The IP cores have been tested at various PCI-SIG PCI Express Compliance Workshops in 2005–2009 with Arria GX, Arria II GX, Cyclone IV GX, Stratix II GX, and Stratix IV GX devices and various external PHYs ...

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... For the hard IP implementation, the speed grades listed are the only speed grades that close timing. When the internal clock frequency is 125 MHz or 250 MHz, Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to Speed ...

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... December 2010 Altera Corporation Chapter 1: Datasheet Recommended Speed Grades Recommended Speed Grades (2) –4,–5,–6 –4,–5,–6 –4,–5,–6 –4,–5,–6 -3, -4 -3, -4 ...

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... The RX Buffer and Retry Buffer ECC options are only available in the hard IP implementation. (2) This is a power-saving mode of operation. (3) Final results pending characterization by Altera for speed grades -2, -3, and -4. Refer to the .fit.rpt file generated by the Quartus II software. (4) Closing timing for the –3 speed grades in the provided endpoint example design requires seed sweeping. ...

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... After you purchase a license for the PCI Express IP core, you can request a license file from the Altera licensing website at (www.altera.com/licensing) and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have internet access, contact your local Altera representative. ...

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... The parameters chosen in this chapter are the same as those chosen in the the Altera website. If you choose the parameters specified in this chapter, you can run all of the tests included in the following sections show you how to instantiate the PCI Express IP core by completing the following steps: 1 ...

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... PCI Express hard IP Stratix IV GX serial Use default settings. ×8 100 MHz Avalon-ST 128 -bit Native Endpoint 2.0 250 MHz Gen 2 (5.0 Gbps) 64 bits Disable Chapter 2: Getting Started Parameterize the PCI Express Parameters, EDA Tools and Summary Tabs Value December 2010 Altera Corporation ...

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... Table 2–2. PCI Registers (Part PCI Base Registers (Type 0 Configuration Space) BAR Register Name Device ID Subsystem ID Revision ID December 2010 Altera Corporation Figure 2–2. Bar2 or Bar3 is required. BAR TYPE 32-Bit Non-Prefetchable Memory 32-Bit Non-Prefetchable Memory 32-bit Non-Prefetchable Memory PCI Read-Only Registers Value 0xE001 ...

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... ABCD Error Reporting Off Off Off Off MSI Capabilities 4 On Link Capabilities On Off Off 0x01 Slot Capabilities Off 0x0000000 MSI-X Capabilities Off 0x000 0x00000000 0 0x00000000 0 Chapter 2: Getting Started Parameterize the PCI Express provides the correct settings Value December 2010 Altera Corporation ...

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... RX buffer space. Figure 2–3. Credit Allocation Table (Read-Only) 13. Click Next to display the Power Management page. correct settings for this page. Table 2–5. Power Management Parameters (Part Idle threshold for L0s entry December 2010 Altera Corporation Parameter 512 bytes 1 None On 16 KBytes ...

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... PCI Express Compiler User Guide Parameter < Number of fast training sequences (N_FTS) Gen2: 255 Gen2: 255 4 L1s Active State Power Management (ASPM) Off < 1 µs > 64 µs > 64 µs Chapter 15, Testbench and Design Chapter 2: Getting Started View Generated Files Value Example. December 2010 Altera Corporation ...

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... Figure 2–4: (1) The chaining_dma directory contains the Quartus II project and settings files. (2) <variation>_plus.v is only available for the hard IP implementation. December 2010 Altera Corporation <working_dir> <variation>.v = top.v, the parameterized PCI Express IP Core <variation>.sdc = top.sdc, the timing constraints file <variation>.tcl = top.tcl, general Quartus II settings ...

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... PCI Express IP Core Endpoint Application Layer Example Traffic Control/Virtual Channel Mapping Request/Completion Routing RC DMA DMA Slave Write Read (Optional) Endpoint Memory (32 KBytes) Design. You can download the required Chapter 2: Getting Started View Generated Files product page. This December 2010 Altera Corporation ...

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... INFO: 11276 ns RP LTSSM State: CONFIG.IDLE # INFO: 11356 ns RP LTSSM State INFO: 11580 ns EP LTSSM State: L0 December 2010 Altera Corporation illustrates, the scripts to run the simulation files are located in the shows the a partial transcript from a successful simulation. As this 2–9 ® software. ...

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... INFO: 32976 ns msi_expected = 0xB0FD PCI Express Compiler User Guide Polling RC Address0000090C Polling RC Address0000090C Polling RC Address0000090C Received DMA Read MSI(0000) : B0FC Chapter 2: Getting Started Simulate the Design current data (0000FADE) current data (00000000) current data (00000002) December 2010 Altera Corporation ...

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... INFO: 40010 ns Passed: 0036 same bytes in BFM mem addr 0x00000040 and 0x00000840 # INFO: 40482 ns Passed: 0040 same bytes in BFM mem addr 0x00000040 and 0x00000840 # SUCCESS: Simulation stopped due to successful completion! December 2010 Altera Corporation Polling RC Address0000080C Polling RC Address0000080C Received DMA Write MSI(0000) : B0FD Polling RC Address0000080C 2– ...

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... Virtual pin assignments allow you to avoid making specific pin assignments for top-level signals while you are simulating and not yet ready to map the design to hardware. This file is the Synopsys Design Constraints File (.sdc) which includes timing constraints. December 2010 Altera Corporation ...

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... PIN_AR38 -to rx_in1 set_location_assignment PIN_AJ38 -to rx_in2 set_location_assignment PIN_AG38 -to rx_in3 set_location_assignment PIN_AE38 -to rx_in4 set_location_assignment PIN_AC38 -to rx_in5 set_location_assignment PIN_U38 -to rx_in6 set_location_assignment PIN_R38 -to rx_in7 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to free_100MHz -disable December 2010 Altera Corporation illustrates the Synopsys timing constraints. 2–13 PCI Express Compiler User Guide ...

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... IO_STANDARD "2.5 V" -to lane_active_led[2] set_instance_assignment -name IO_STANDARD "2.5 V" -to lane_active_led[3] set_instance_assignment -name IO_STANDARD "2.5 V" -to L0_led set_instance_assignment -name IO_STANDARD "2.5 V" -to alive_led set_instance_assignment -name IO_STANDARD "2.5 V" -to comp_led PCI Express Compiler User Guide Chapter 2: Getting Started Constrain the Design December 2010 Altera Corporation ...

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... To use this example design as the basis of your own design, replace the endpoint application layer example shown in design. Then, modify the BFM driver to generate the transactions needed to test your application layer. December 2010 Altera Corporation Figure 2–4. After you have fully tested your Figure 2–5 ...

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... PCI Express Compiler User Guide Chapter 2: Getting Started Reusing the Example Design December 2010 Altera Corporation ...

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... Stratix II GX Stratix IV GX PHY type Stratix V GX Stratix V GX CVP Cyclone IV GX December 2010 Altera Corporation Table 3–1 describes these settings. Description The hard IP implementation uses embedded dedicated logic to implement the PCI Express protocol stack, including the physical layer, data link layer, and transaction layer. ...

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... You do not need to change any of the PIPE PHY for Stratix V GX transceiver. To learn more about this IP core, refer to the “PCI Express PIPE PHY IP User Guide “ in the Altera Transceiver PHY IP Core User Guide. Specifies the maximum number of lanes supported. The ×8 ...

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... Avalon-MM. 128-bit Avalon-ST is only available when using the hard IP implementation. Specifies the port type. Altera recommends Native Endpoint for all new endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The SOPC Builder design flow only supports Native Endpoint and the Avalon-MM interface to the user application ...

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... Soft IP ×8 test_out width: None, 9 bits, or 128 bits Most of these signals are reserved. Refer to for more information. Altera recommends the 64-bit width for the hard IP implementation. Enables reconfiguration of the hard IP PCI Express read-only configuration registers. This parameter is only available for the hard IP implementation ...

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... BAR sizes and Avalon-MM base addresses or to enter the values manually. The Avalon-MM address is the translated base address corresponding to a BAR hit of a received request from PCI Express link. Altera recommends using the Auto setting. However, if you decide to enter the address ...

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... Specifies what address widths are supported for the prefetchable memory base register and prefetchable memory limit register. Table 3–3. Some of these parameters are Header. The byte offset within the indicates the parameter address. Chapter 3: Parameter Settings Capabilities Parameters PCI Express Base December 2010 Altera Corporation ...

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... On/Off disable 0x0A8 Completion timeout range Ranges A–D December 2010 Altera Corporation Description Device Capabilities 0x084 Indicates the number of tags supported for non-posted requests transmitted by the application layer. The following options are available: Hard IP tags for ×1, ×4, and ×8 Soft IP: 4– ...

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... Ranges B and C 0x0111b Ranges A, B, and C 0x1110b Ranges B, C and D 0x1111b Ranges and D This setting is not available for PCIe version 1.0. All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms. Error Reporting 0x800–0x834 Implements the advanced error reporting (AER) capability ...

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... Offset MSI-X Table BAR Indicator <5–1>:0 BIR December 2010 Altera Corporation Description Link Capabilities 0x090 Indicates if the common reference clock supplied by the system is used as the reference clock for the PHY. This parameter sets the read-only value of the slot clock configuration bit in the link status register ...

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... The hard IP retry buffer is fixed at 4 KBytes for Arria II GX and Cyclone IV GX devices KBytes for Stratix IV GX devices, and at 8 KBytes for Stratix V GX devices. Chapter 3: Parameter Settings Buffer Setup PCI Express Base “Transmit for more information. This parameter sets December 2010 Altera Corporation ...

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... High, received Medium, Low completions December 2010 Altera Corporation Description Set the maximum number of packets that can be stored in the retry buffer. For the hard IP implementation this parameter is set to 64. Low—Provides the minimal amount of space for desired traffic. Select this option when the throughput of the received requests is not critical to the system design ...

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... Sets the read-only value of the endpoint L0s acceptable latency field of the device capabilities register (0x084). This value should be based on how much latency the application layer can tolerate. This setting is disabled for root ports. Chapter 3: Parameter Settings Power Management Description December 2010 Altera Corporation ...

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... Common clock L1 Exit Latency < 1µs to > 64 µs Separate clock December 2010 Altera Corporation Number of fast training sequences (N_FTS) Indicates the number of fast training sequences needed in common clock mode. The number of fast training sequences required is transmitted to the other end of the link during link initialization and is also used to calculate the L0s exit latency field of the device capabilities register (0x084) ...

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... Avalon-MM CRA Port be enabled. Use several address translation table entries to avoid updating a table entry before outstanding requests complete. Fixed translation table—Configures the address translation table contents to hardwired fixed values at the time of system generation. Chapter 3: Parameter Settings Avalon-MM Configuration Table 3–6 December 2010 Altera Corporation ...

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... Memory Type Enable Avalon-MM CRA port Disable December 2010 Altera Corporation Description Sets Avalon-MM-to-PCI Express address translation windows and size. Specifies the number of PCI Express base address pages of memory that the bridge can access. This value corresponds to the number of entries in the address translation table. The Avalon address range is segmented into one or more equal-sized pages that are individually mapped to PCI Express addresses ...

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... PCI Express Compiler User Guide Chapter 3: Parameter Settings Avalon-MM Configuration December 2010 Altera Corporation ...

Page 59

... PCI Express soft IP endpoints comply with the 1.1. The PCI Express hard IP endpoint and root port comply with the Specification 1.1. 2.0, or December 2010 Altera Corporation 4. IP Core Architecture PCI Express Base Specification 1.0a, or 2.1. PCI Express Base ...

Page 60

... PCI Express IP Core Tx Port Avalon-ST Interface or Avalon-MM Interface Rx Port or Data/Descriptor Interface Application Interfaces This chapter provides an overview of the architecture of the Altera PCI Express IP core. It includes the following sections: Application Interfaces ■ ■ Transaction Layer ■ Data Link Layer ■ Physical Layer PCI Express Avalon-MM Bridge ■ ...

Page 61

... The hard IP implementation includes dedicated clock domain crossing logic between the PHYMAC and data link layers. In the soft IP implementation you can specify one or two clock domains for the IP core. December 2010 Altera Corporation With information sent The data link layer by the application ...

Page 62

... Space Reconfig Clock & Reset Selection Data Link Transaction Layer Layer (TL) (DLL) Test Chapter 4: IP Core Architecture Application Interfaces Avalon-ST Rx Avalon-ST Tx Adapter Side Band LMI LMI PCIe Reconfig Block (Avalon-MM) Avalon-ST Rx Avalon-ST Tx Adapter Side Band Test_in/Test_out December 2010 Altera Corporation ...

Page 63

... Lanes ×1 ×2 ×4 Lanes ×1 ×4 ×8 December 2010 Altera Corporation Hard IP Implementation— Stratix V GX Gen1 125 MHz @ 64 bits 125 MHz @ 64 bits 250 MHz @ 64 bits or 125 MHz @ 128 bits Gen1 62.5 MHz @ 64 bits or 125 MHz @ 64 bits 125 MHz @ 64 bits 250 MHz @ 64 bits or 125 MHz @ 128 bits Hard IP Implementation— ...

Page 64

... The application waits for the TLPs to cross the Avalon-ST TX interface. PCI Express Compiler User Guide Figure 4–4. For more detailed information, refer to and “64-, 128-, or 256-Bit Avalon-ST TX Port” on Chapter 4: IP Core Architecture Application Interfaces “64-, 128-, or 256-Bit December 2010 Altera Corporation ...

Page 65

... When it is necessary to send an MSI request after a specific TX packet, you can use the TX FIFO empty flag to determine when the IP core receives the TX packet. December 2010 Altera Corporation “Component Specific for more information about the signals in this “LMI Signals—Hard IP Implementation” on PCI Express Compiler User Guide 4– ...

Page 66

... PCI Express Compiler User Guide illustrates the Avalon-ST TX and MSI datapaths. tx_cred0 for Completion and Posted Requests (from Transaction Layter) tx_cred0 for Non-Posted Requests Non-Posted Credits tx_st_data0 Layer tx_fifo_empty0 tx_fifo_wrptr0 tx_fifo_rdptr0 app_msi_req Chapter 4: IP Core Architecture Application Interfaces To Transaction Layer FIFO December 2010 Altera Corporation ...

Page 67

... Within each virtual channel, transaction layer packets are stored in a specific part of the receive buffer depending on the type of transaction (posted, non-posted, and completion). December 2010 Altera Corporation With information sent The data link layer by the application ensures packet ...

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... Packet FIFO Flow Control Update Receive Buffer Tx Flow Control Credits Posted & Completion Non-Posted Transaction Layer Packet FIFO Rx Transaction Flow Control Update Layer Packet Chapter 4: IP Core Architecture Transaction Layer Transmit Data Path Configuration Space Receive Data Path December 2010 Altera Corporation ...

Page 69

... Refer To “Configuration Space Register Content” on page 6–1 Express Base Specification 1.0a, 1.1 or 2.0 December 2010 Altera Corporation 2.0. You can use the settings on the Buffer Setup page, 3–10. PCI Express Base Specification Revision 1.0a, 1.1, 2.0, or for the complete content of these registers. ...

Page 70

... DLLP Tx Arbitration Generator Ack/Nack Packets Power Management Function DLLP Checker Chapter 4: IP Core Architecture Data Link Layer To Physical Layer Tx Packets Transmit Data Path Control Data Link Control & Status & Management State Machine Receive Data Path Rx Packets December 2010 Altera Corporation ...

Page 71

... The physical layer connects to the link through a high-speed SERDES interface running at 2.5 Gbps for Gen1 implementations and at 2.5 or 5.0 Gbps for Gen2 implementations. Only the hard IP implementation supports the Gen2 rate. The physical layer is responsible for the following actions: December 2010 Altera Corporation 4–13 PCI Express Compiler User Guide ...

Page 72

... LTSSM PIPE State Machine Emulation Logic 8B10B Elastic Decoder Rx MAC Lane 8B10B Elastic Decoder Rx MAC Lane Figure 4–9): Chapter 4: IP Core Architecture Physical Layer To Link Tx+ / Tx- Transmit Data Path Tx+ / Tx- Rx+ / Rx- Buffer Receive Data Path Rx+ / Rx- Buffer December 2010 Altera Corporation ...

Page 73

... Each symbol includes eight data bits and one control bit. The FTS, COM, and SKP symbols are discarded by the FIFO; the PAD and IDL are replaced by D0.0 data. When all eight FIFOs contain data, a read can occur. December 2010 Altera Corporation 4–15 PCI Express Compiler User Guide ...

Page 74

... RX Master Module—This 64-bit bursting Avalon-MM master port propagates PCI Express requests, converting them to bursting read or write requests to the system interconnect fabric. PCI Express Compiler User Guide Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge Figure 4–10, provides December 2010 Altera Corporation ...

Page 75

... Avalon-MM Rx Master Avalon-MM Rx Read Response The PCI Express Avalon-MM bridge supports the following TLPs: ■ Memory write requests December 2010 Altera Corporation PCI Express MegaCore Function PCI Express Avalon-MM Bridge PCI Express Clock Domain MSI or Legacy Interrupt Sync Reg (CSR) Generator ...

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... The Avalon-MM byte enable must be asserted in the first qword of the burst. ■ All subsequent byte enables must be asserted until the deasserting byte enable. ■ PCI Express Compiler User Guide Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge December 2010 Altera Corporation ...

Page 77

... The Avalon-MM byte enable may deassert, but only in the last qword of the burst improve PCI Express throughput, Altera recommends using an Avalon-MM burst master without any byte-enable restrictions. Avalon-MM-to-PCI Express Upstream Read Requests The PCI Express Avalon-MM bridge converts read requests from the system ...

Page 78

... Description Write full 32 bits Write the lower 2 bytes Write the upper 2 bytes Write byte 0 only Write byte 1 only Write byte 2 only Write byte 3 only 3–10. Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge “Buffer Setup December 2010 Altera Corporation ...

Page 79

... LSB bits remain unchanged. The number of MSB bits to be replaced is calculated based on the total address space of the upstream PCI Express devices that the PCI Express IP core can access. December 2010 Altera Corporation depicts the PCI Express Avalon-MM bridge address (Note 1) Low address bits unchanged ...

Page 80

... Address Translation Table” on page PCI Express Compiler User Guide 4–23. The most significant bits of the Avalon-MM address are Figure 4–12 are: 6–9. Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge “Avalon-MM-to-PCI Express December 2010 Altera Corporation ...

Page 81

... For interrupts due to the RXmIrq_i signal, the interrupt status should be cleared in the other Avalon peripheral that sourced the interrupt. This sequence prevents interrupts from being lost during interrupt servicing. December 2010 Altera Corporation (Note 1) (2) (3) (4) (5) Low address bits unchanged ...

Page 82

... DEASSERT_INTA Message Sent) SET CLR MSI Enable (Table 11–1) can be used to disable legacy interrupts. The MSI enable 11–5, can be used to enable MSI interrupts. Only one type of Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge MSI Request “PCI and December 2010 Altera Corporation ...

Page 83

... It supports memory reads and writes of a single dword. It generates a completion with Completer Abort (CA) status for reads greater than four bytes and discards all write data without further action for write requests greater than four bytes. December 2010 Altera Corporation Bridge Avalon-MM PCIe Rx ...

Page 84

... Sending an MSI interrupt instead of a legacy interrupt Loss of an interrupt request ■ PCI Express Compiler User Guide Chapter 4: IP Core Architecture Completer Only PCI Express Endpoint Single DWord Avalon Interface Specifications. Figure 4–14. You must allow time for the Bridge December 2010 Altera Corporation ...

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... Signals in the Completer-Only, Single Dword, IP Core with Avalon-MM Interface 1 Altera does not recommend the Descriptor/Data interface for new designs. Avalon-ST Interface The main functional differences between the hard IP and soft IP implementations using an Avalon-ST interface are the configuration and clocking schemes. In addition, the hard IP implementation offers a 128-bit Avalon-ST bus for some configurations ...

Page 86

... PHY 8-bit PIPE PIPE Interface Simulation Only Repeated for PIPE Lanes 1-7 Interface 8-bit Simulation PIPE Only (2) pipe_rstn pipe_txclk pclk_in Clocks - clk250_out Simulation clk500_out Only Config Config lmi_rden lmi_wren LMI LMI lmi_ack Test Interface Test Interface December 2010 Altera Corporation ...

Page 87

... Arria GX. For Stratix IV GX, <n> for ×1 and ×4 IP cores and <n> the ×8 IP core. (2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> For Stratix IV GX, <n> December 2010 Altera Corporation Signals in the PCI Express Hard IP Core rx_st_ready <n> ...

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... Chapter 5: IP Core Interfaces Avalon-ST Interface Transceiver Control Serial IF to PIPE for internal PHY Repeated for Lanes 1-3 in 16-bit x4 MegaCore PIPE for x1 and x4 for external PHY Repeated for 8-bit Lanes 1-7 in PIPE x8 MegaCore for x8 Test Interface December 2010 Altera Corporation ...

Page 89

... Clocks <variant>_plus Reset & Link <variant> Training Reconfiguration Block (optional) ECC Error Interrupts (Root Port) Completion Interface December 2010 Altera Corporation Signals in the PCI Express Hard IP Core Stratix V rx_st_ready (1) reconfig_fromgxb[:0] rx_st_valid reconfig_togxb[:0] (2) rx_st_data[63:0], [127:0], [255:0] rx_st_sop rx_st_eop gxb_powerdown rx_st_empty rx_st_err ...

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... Control” on page 5–53 v “Serial Interface Signals” on page 5–55 v “PIPE Interface Signals” on page 5–56 Test “Test Interface Signals—Hard IP Implementation” on page 5–59 v “Test Interface Signals—Soft IP Implementation” on page 5–60 Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

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... O rx_st_empty<n> rx_st_err<n> rx_st_mask<n> December 2010 Altera Corporation Avalon-ST Description Type Indicates that The application is ready to accept data. The ready application deasserts this signal to throttle the data stream. Clocks rx_st_data<n> into application. Deasserts within 3 clocks of rx_st_ready<n> deassertion and reasserts within 3 clocks of rx_st_ready<n> assertion if more data is available valid to send ...

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... Generates even parity on the entire TLP when parity is enabled. specific Available for Stratix V devices only. Chapter 5: IP Core Interfaces Avalon-ST Interface and Figure 5–10 illustrate the timing Figure 5–6 on December 2010 Altera Corporation ...

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... In this example, the byte address is unaligned and ends with 0x4, causing the first data to correspond to rx_st_data[63:32]. f For more information about the Avalon-ST protocol, refer to the Specifications. December 2010 Altera Corporation PCB Memory 64 bits . . . ...

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... PCI Express Compiler User Guide Avalon Interface Data0 Header2 F Data1 Data3 Header2 Data0 Data2 header3 data1 header2 data0 December 2010 Altera Corporation Chapter 5: IP Core Interfaces Avalon-ST Interface Specifications, is big Data2 Data1 ...

Page 95

... TLPs with a three dword header and qword aligned addresses. Figure 5–10. 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-DWord Header TLPs with QWord Aligned Addresses clk rx_st_valid rx_st_data[127:96] rx_st_data[95:64] rx_st_data[63:32] rx_st_data[31:0] rx_st_bardec[7:0] rx_st_sop rx_st_eop rx_st_empty December 2010 Altera Corporation header3 data0 header2 10 C data3 header2 data2 header1 data1 header0 ...

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... Header 0 Data 1 Data (n-1) Header 3 Data 2 Header 2 Data 1 Data n Header 1 Data 0 Data n-1 Header 0 Data n-2 Header3 Data3 Data n Header 2 Data 2 Data n-1 Header 1 Data 1 Data n-2 Header 0 Data 0 Data n-3 Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

Page 97

... Altera recommends a readyLatency of 2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals other delays are added to the ready-valid latency, this corresponds to a readyLatency of 2. ...

Page 98

... IP and 2 cycles for the hard IP implementation. Refer to the timing of this signal. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid I valid signals other delays are added to the ready-valid latency, this corresponds to a readyLatency of 2 Data for transmission ...

Page 99

... December 2010 Altera Corporation Avalon-ST Type This is the read pointer for the adaptor TX FIFO. Does not component O apply to Stratix V devices. specific This is the write pointer for the adaptor TX FIFO. Does not component O apply to Stratix V devices. ...

Page 100

... Header credit limit for the FC completions. Each credit is component O 20 bytes. specific component Generates even parity on the entire TLP when parity is o specific enabled. Available for Stratix V GX devices only. Chapter 5: IP Core Interfaces Avalon-ST Interface Description December 2010 Altera Corporation ...

Page 101

... To be Avalon-ST compliant, you must use a readyLatency for hard IP implementation, and a readyLatency for the soft IP implementation. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals other delays are added to the ready-valid latency, this corresponds to a readyLatency of 2. ...

Page 102

... Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} (6) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4} PCI Express Compiler User Guide illustrates the storage of non-qword aligned data.) 2 Header1 Data0 Header0 Header2 2 Header1 Header3 Header0 Header2 Chapter 5: IP Core Interfaces Avalon-ST Interface 3 Data2 Data1 3 Data1 Data0 December 2010 Altera Corporation ...

Page 103

... Figure 5–20. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-DWord Header TLP with non-QWord Aligned Address clk tx_st_valid tx_st_data[127:96] tx_st_data[95:64] tx_st_data[63:32] tx_st_data[31:0] tx_st_sop tx_st_err tx_st_eop tx_st_empty December 2010 Altera Corporation Header 1 Header3 Data0 Data2 Header 0 Header2 Data1 Data3 Header2 Data 2 Header1 ...

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... PCI Express Compiler User Guide Header 3 Data 3 Header 2 Data 2 Header 1 Data 1 Header 0 Data 0 Data 4 Header 3 Data 2 Data n Header 2 Data 1 Data n-1 Header 1 Data 0 Data n-2 Header 0 Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

Page 105

... Figure 5–24. Location of Headers and Data for Avalon-ST 256-Bit Interface 0 4DW header, 4DW header, D3 Aligned data Unaligned data 255 December 2010 Altera Corporation Aligned Data Header 1 Header 0 Header 1 Header 0 XXXXXXXX Header 2 XXXXXXXX Data 0 XXXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXX 01 0 3DW header Aligned data ...

Page 106

... ECRC would correspond to Data0 in these figures. PCI Express Compiler User Guide response_time cycle 1 cycle 2 cycle 3 cycle 4 through Figure 5–13 on page 5–12 Figure 5–16 on page 5–18 Chapter 5: IP Core Interfaces Avalon-ST Interface cycle n illustrate the position of through Figure 5–22 on December 2010 Altera Corporation ...

Page 107

... Output from the ×8 IP core. 250 MHz clock output derived from the refclk input. This signal O clk250_out is only on the ×8 IP core. Note to Table 5–6: (1) Refer to Figure 7–9 on page 7–12 December 2010 Altera Corporation (Note 1) Description Table 12–4. 7–9. for a complete description of the clock interface (Note 1) Description 5– ...

Page 108

... L1.entry ■ dl_ltssm[4:0] 10111: L1.idle ■ O 11000: L2.idle (continued) ■ 11001: L2.transmit.wake ■ PCI Express Compiler User Guide Description <variant>_plus.v or .vhd Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

Page 109

... IP implementation). This signal is active low and otherwise remains high. In Gen1 and Gen2, the hotrst_exit signal is asserted 1 ms after the dl_ltssm signal exit from the hot.reset state December 2010 Altera Corporation Description PCI Express Card Electromechanical Specification 2.0 for a timing diagram illustrating the use of this signal. ...

Page 110

... Stratix V devices. <variant> .vhd <variant> _core.v or .vhd altpcie_hip_pipen1b.v or .vhd npor SERDES Reset State Machine Configuration Space Sticky Registers Configuration Space crst Non-Sticky Registers srst Datapath State Machines of MegaCore Fucntion Chapter 5: IP Core Interfaces Avalon-ST Interface “Reset December 2010 Altera Corporation ...

Page 111

... Reset Details for Stratix V Devices Figure 5–27 provides a simplified view of the logic controlled by the reset signals in Stratix V devices. Figure 5–27. Reset Domains for Stratix V Devices pld_clrpmapcship December 2010 Altera Corporation <variant> .vhd <variant> _core.v or .vhd altpcie_hip_256_pipen1b.v perst_n SERDES Reset State Machine ...

Page 112

... The ability for Gen2-capable designs to begin link initialization and ultimately to reach L0 before the FPGA is configured is pending device characterization. For additional information about reset in Stratix V devices refer to Devices” on page PCI Express Compiler User Guide illustrates, configuration includes the following steps: 100 ms detect detect.active polling.active 7–4. Chapter 5: IP Core Interfaces Avalon-ST Interface L0 “Reset in Stratix V December 2010 Altera Corporation ...

Page 113

... It is included on the app_int_ack Avalon-ST interface for the hard IP implementation and the ×1 and ×4 soft IP implementation. Refer to timing information. December 2010 Altera Corporation (Note 1) (Note 2) I/O Description Indicates a correctable error in the RX buffer for the corresponding virtual O channel ...

Page 114

... MSI requested ■ 101: 32 MSI requested ■ 110: Reserved ■ If set to 0, this component is not permitted to use MSI. Chapter 5: IP Core Interfaces Avalon-ST Interface multiple message MSI capable enable — PCI Local Bus Specification, Rev. 3.0. Per December 2010 Altera Corporation ...

Page 115

... The tl_cfg_ctl signal is multiplexed and contains the contents of the configuration space 32 0 registers as shown in this table. This register carries data that updates every 8 tl_cfg_ctl core_clk cycles. December 2010 Altera Corporation Description 2.0. in the root control register. 5–34. PCI Express Base Specification for more information about the hot plug signals. ...

Page 116

... For endpoint variations the hpg_ctrler Slot capability register parameter should be set to 0. parameter should be set to 0. Chapter 5: IP Core Interfaces Avalon-ST Interface Enable slot Enable slot capability and Slot capability Slot capability register parameter Slot Slot capability register December 2010 Altera Corporation ...

Page 117

... Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 128-bit interface. Figure 5–33. tl_cfg_sts Timing (Hard IP Implementation) core_clk pld_clk 128-bit mode tl_cfg_sts[52:0] tl_cfg_sts_wr December 2010 Altera Corporation data0 addr0 core_clk data0 addr0 data0 data0 5– ...

Page 118

... This register carries data that updates every tl_cfg_ctl pld_clk cycle. PCI Express Compiler User Guide Figure 5–30 and Figure 5–32 is used. The multicycle setup and hold 5–36. The information updates every pld_clk cycle. Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

Page 119

... If there is not a power controller for this slot, this bit should be hardwired to 0 and the Power Controller Present bit (bit[1]) in the parameter should be set to 0. December 2010 Altera Corporation tl_cfg_sts[52:49]= cfg_devcsr[19:16]error detection signal as follows: [correctable error reporting, enable, non-fatal error reporting ...

Page 120

... Max Payload cfg_prmcsr[15:0] cfg_secbus[7:0] cfg_io_bas[19:0] cfg_io_lim[19:0] cfg_np_bas[11:0] cfg_pr_bas[31:0] 20’h00000 cfg_pr_lim[31:0] 20’h00000 cfg_pmcsr[31:0] cfg_tcvcmap[23:0] Chapter 5: IP Core Interfaces Avalon-ST Interface data4 data5 data6 addr4 addr5 addr6 data5 data6 (Note 1) 7:0 cfg_dev2csr[15:0] cfg_slotcsr[15:0] cfg_link2csr[15:0] cfg_rootcsr[7:0] cfg_subbus[7:0] cfg_np_lim[11:0] cfg_pr_bas[43:32] cfg_pr_lim[43:32] cfg_msicsr[15:0] December 2010 Altera Corporation ...

Page 121

... O cfg_slotcsr 32 O cfg_linkcsr, cfg_link2csr 16 O cfg_prmcsr December 2010 Altera Corporation 23:16 3’b000 PCI Express Base Specification.(3’b000–3b101 correspond to 128–4096 bytes). Description cfg_devcsr[31:16]is status and cfg_devcsr[15:0] is device control for the PCI Express capability structure. cft_dev2csr[31:16] is status 2 and cfg_dev2csr[15:0] is device control 2 for the PCI Express capability structure. ...

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... EXP ROM Table 3–2 on page 3–5 EXP ROM Table 6–3 on page 6–3 0x024 and Table 3–2 Prefetchable memory Table 6–3 on page 6–3 0x024 Table 3–2 Prefetchable memory Table 6–6 on page 6–4 0x07C Table 6–5 on page 6–4 0x068 December 2010 Altera Corporation ...

Page 123

... Device number. Configuration primary control status register. The content of this register controls the PCI O cfg_prmcsr[31:0] status. December 2010 Altera Corporation Description MSI message control. Duplicated for each function implementing MSI. Configuration traffic class (TC)/virtual channel (VC) mapping. The application layer uses this signal to generate a transaction layer packet mapped to the appropriate virtual channel based on the traffic class of the packet ...

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... LMI writes log error descriptor information in the AER header log registers. These writes record completion errors as described in ST Interface” on page Altera does not recommend using the LMI bus to access other configuration space registers for the following reasons: ■ LMI write—An LMI write updates the internally captured bus and device numbers incorrectly ...

Page 125

... Enable for the PCIe Reconfig option on the System Settings page of the MegaWizard interface. You can use this interface to change the value of configuration registers that are read-only at run time. For a description of the registers available via this interface refer to the section entitled, Cancellation. December 2010 Altera Corporation Width Dir Description 32 ...

Page 126

... Reconfiguration clock for the hard IP implementation. This I clock should not exceed 50MHz. Active-low Avalon-MM reset. Resets all of the dynamic I reconfiguration registers to their default values as described in Table 13–1 on page 13–2. Description Table 5–21 December 2010 Altera Corporation Chapter 5: IP Core Interfaces Avalon-ST Interface and Table 5–22 for 5–31. ...

Page 127

... When this signal is set indicates that the function would normally assert the PME# [15] PME_status message independently of the state of the PME_en bit. This field indicates the scaling factor when interpreting the value retrieved from the data [14:13] data_scale register. This field is read-only. December 2010 Altera Corporation Description 1413 129 data_scale data_select Description — ...

Page 128

... Refer to errors that are automatically detected and handled by the IP core. PCI Express Compiler User Guide Description — clk PCI Express Base Specification. Note that the application is Chapter 12, Error Handling Chapter 5: IP Core Interfaces Avalon-ST Interface for information on December 2010 Altera Corporation ...

Page 129

... Table 5–23. Completion Signals for the Avalon-ST Interface (Part Signal I/O I cpl_err[6:0] I December 2010 Altera Corporation 2.0. Description Completion error. This signal reports completion errors to the configuration space. When an error occurs, the appropriate signal is asserted for one cycle. cpl_err[0]: Completion timeout error with recovery. This signal should be ■ ...

Page 130

... If this signal is asserted and low power mode is requested, the IP core waits for the deassertion of this signal before transitioning into low-power state. Chapter 5: IP Core Interfaces Avalon-MM Application Interface for more December 2010 Altera Corporation ...

Page 131

... Arria GX. For Stratix IV GX, <n> for ×1 and ×4 IP cores and <n> the ×8 IP core. (2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> For Stratix IV GX, <n> (3) Signals in blue are for simulation only. December 2010 Altera Corporation Signals in the PCI Express MegaCore Function with Avalon-MM Interface (1) reconfig_fromgxb[ < ...

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... Chapter 5: IP Core Interfaces Avalon-MM Application Interface Transceiver Control 1-Bit Serial Soft IP Implementation 16-Bit PIPE for x1 and x4 (Repeat for lanes 1-3 in x4) Hard IP Implementation 8-Bit PIPE Simulation Only (3) Test Interface December 2010 Altera Corporation ...

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... CraAddress_i[11:0] I CraByteEnable_i[3:0] I CraChipSelect_i I CraRead_i I CraWrite_i I CraWriteData_i[31:0] December 2010 Altera Corporation Completer Only Logical — “32-Bit Non-bursting Avalon-MM CRA Slave Signals” on page 5–49 v “RX Avalon-MM Master Signals” on page 5–50 — “64-Bit Bursting TX Avalon-MM Slave Signals” on page 5–50 v “Clock Signals” on page 5–51 v “ ...

Page 134

... PCI Express IP core. Requests from the system interconnect fabric are translated into PCI Express request packets. Incoming requests can KByte s in size. For better performance, Altera recommends using smaller read request size (a maximum 512 bytes). PCI Express Compiler User Guide ...

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... AvlClk_i Refer to “Avalon-MM Interface–Hard IP and Soft IP Implementations” on page 7–14 for a complete explanation of the clocking scheme. December 2010 Altera Corporation I/O Description The system interconnect fabric asserts this signal to select the TX I slave port. Read request asserted by the system interconnect fabric to I request a read ...

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... PCI Express MegaCore Function Reset Synchronizer (to PCI Express Clock) RxmResetRequest_o npor PCIe_rstn Table 5–7. Chapter 5: IP Core Interfaces Avalon-MM Application Interface PCI Express Avalon-MM Bridge Rstn_i Transaction Layer Data Link Layer Physical Layer npor srst crst l2_exit hotrst_exit dlup_exit dl_ltssm[4:0] December 2010 Altera Corporation ...

Page 137

... I/O I cal_blk_clk I gxb_powerdown December 2010 Altera Corporation Description The cal_blk_clk input signal is connected to the transceiver calibration block clock (cal_blk_clk) input. All instances of transceivers in the same device must have their cal_blk_clk inputs connected to the same signal because there is only one calibration block per device. This input should be connected to a ...

Page 138

... Stratix II GX ALT2GXB_RECONFIG Megafunction Transceiver Configuration Guide in volume 3 of the Chapter 5: IP Core Interfaces Physical Layer Interface Signals Stratix II GX 13–9. Stratix V GX Stratix II GX Stratix IV GX (1) Yes Yes No Yes Yes No Yes Yes No Yes Yes No Stratix IV Device as December 2010 Altera Corporation ...

Page 139

... When simulating, you can set this signal to indicate which interface is used for the simulation. When compiling your design for an Altera device, set this signal to 0. Reset signal to reset the PLL associated with the PCI Express IP core. Asserted to indicate that the IP core PLL has locked. May be used to implement an optional reset controller to guarantee that the external PHY and PLL are stable before bringing the PCI Express IP core out of reset ...

Page 140

... First PCI Express Express (PIPE) (PIPE) Transceiver Block GXBR0 x8 Link x8 Link for pin-out tables for all Altera devices in Arria GX Device Handbook, Volume 2 of Stratix II GX Transceiver User Guide, or Volume 2 of the Table 5–33 Chapter 5: IP Core Interfaces Physical Layer Interface Signals ...

Page 141

... December 2010 Altera Corporation Chapter 14, External PHYs for descriptions of the slightly modified I/O Transmit data <n> (2 symbols on lane <n>). This bus transmits data on lane <n>. The first transmitted symbol is txdata_ext[7:0] and the O second transmitted symbol is txdata0_ext[15:8]. For the 8-bit PIPE mode only txdata< ...

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... IP cores. implementation. c Altera recommends that you use the test_out and test_in signals for debug or non- critical status monitoring purposes such as LED displays of PCIe link status. They should not be used for design function purposes. Use of these signals will make it more difficult to close timing on the design ...

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... Table 5–35: (1) All signals are per lane. (2) Refer to “PIPE Interface Signals” on page 5–57 December 2010 Altera Corporation I/O Description The test_in bus provides runtime control for specific IP core features. For normal operation, this bus can be driven to all 0's. The following bits are defined: [0]— ...

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... The following bits are defined when you choose the larger bus: [7:0]—txdata. ■ [8]—txdatak. ■ [9]—txdetectrx. ■ [10]—txelecidle. ■ [11]—txcompl. ■ [12]—rxpolarity. ■ [14:13]—powerdown. ■ [22:15]—rxdata. ■ [23]—rxdatak. ■ [24]—rxvalid. ■ [63:25]—reserved. ■ Chapter 5: IP Core Interfaces Test Signals December 2010 Altera Corporation ...

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... Virtual channel arbitration table 0x200:0x23C Port VC0 arbitration table (Reserved) 0x240:0x27C Port VC1 arbitration table (Reserved) 0x280:0x2BC Port VC2 arbitration table (Reserved) December 2010 Altera Corporation 6. Register Descriptions depending on the version you specify 23:16 15:8 Table 6–2 for details.) Table 6–3 for details.) Table 6– ...

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... Class code Header Type type) (Port Reserved Subsystem ID 0x00 Chapter 6: Register Descriptions Configuration Space Register Content 15:8 7:0 15:8 7:0 Vendor ID Command Revision ID 0x00 Cache Line Size Subsystem vendor ID Capabilities Pointer Interrupt Pin Interrupt Line PCI Express December 2010 Altera Corporation ...

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... Note to Table 6–4: (1) Refer to Table 6–23 on page 6–12 for a comprehensive list of correspondences between the configuration space registers and the Base Specification 2.0. December 2010 Altera Corporation 23:16 Device ID Status Class code Primary Latency Header Type BAR Table (BAR0) BAR Table (BAR1) ...

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... Reserved Root Status Chapter 6: Register Descriptions Configuration Space Register Content 15:8 7:3 2:0 Capability ID BIR PCI Express 15:8 7:0 Cap ID PCI Express 15:8 7:0 PCI Express Cap ID Device Control Link Control Slot Control Root Control PCI Express December 2010 Altera Corporation ...

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... VC Resource Status Register (0) 0x11C PAT offset 1 (31:24) 0x120 VC Resource Control Register (1) 0x124 VC Resource Status Register (1) ... 0x164 PAT offset 7 (31:24) December 2010 Altera Corporation 31:16 Next Cap Pointer Device Capabilities Link Capabilities Link Status Slot Capabilities Slot Status Root Status Device Capabilities 2 ...

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... However, the regions are designed to enable straight-forward enforcement by processor software. PCI Express Compiler User Guide Chapter 6: Register Descriptions PCI Express Avalon-MM Bridge Control Register Content 23:16 15:8 23:16 15:8 Correctable Error Source ID Register December 2010 Altera Corporation 7:0 7:0 PCI Express ...

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... PCI Express interrupt to be asserted. Table 6–13. Avalon-MM to PCI Express Interrupt Status Register (Part Bit Name 31:24 Reserved 23 A2P_MAILBOX_INT7 22 A2P_MAILBOX_INT6 December 2010 Altera Corporation Table 6–11: Address Space Usage Register Access Description — — RW1C 1 when the A2P_MAILBOX7 is written to ...

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... Description — — Enables generation of PCI Express interrupts when a RW specified mailbox is written external Avalon- MM master. — — Enables generation of PCI Express interrupts when RW RXmlrq_i is asserted — — December 2010 Altera Corporation Chapter 6: Register Descriptions Address: 0x0040 “Generation of PCI Address: 0x0050 ...

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... A2P_MAILBOX5 0x0918 A2P_MAILBOX6 0x091C A2P_MAILBOX7 Avalon-MM-to-PCI Express Address Translation Table The Avalon-MM-to-PCI Express address translation table is writable using the CRA slave port if dynamic translation is enabled. December 2010 Altera Corporation Access Description RW PCI Express-to-Avalon-MM Mailbox 0 RW PCI Express-to-Avalon-MM Mailbox 1 RW PCI Express-to-Avalon-MM Mailbox 2 ...

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... This entry is only implemented if number of table entries is greater than 1. Upper bits of Avalon-MM-to-PCI Express address map entry 1. RW This entry is only implemented if the number of table entries is greater than 1. (Table 3–6 on page Table 6–18. Indication December 2010 Altera Corporation 6–17 bytes wide, Table 6–18 Table 6–18 3–14). If Number ...

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... PCI Express interrupt status register is set to 1. Table 6–21. Avalon-MM-to-PCI Express Mailbox Registers, Read/Write (Part Address Name 0x3A00 A2P_MAILBOX0 0x3A04 A2P _MAILBOX1 December 2010 Altera Corporation (Table 6–19) records the status of all conditions that can Access — RW1C 1 when the P2A_MAILBOX0 is written RW1C ...

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... Type 1 Configuration Space Header MSI and MSI-X Capability Structures MSI and MSI-X Capability Structures PCI Power Management Capability Structure PCI Express Capability Structure PCI Express Capability Structure Chapter 6: Register Descriptions Address Range: 0x3A00-0x3A1F Description Address Range: 0x3800-0x3B1F Description December 2010 Altera Corporation ...

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... Class Code Revision ID BIST Header Type Primary Latency Timer Cache 0x00C Line Size 0x010 Base Address 0 December 2010 Altera Corporation Corresponding Section in PCIe Specification Virtual Channel Capability VC Arbitration Table Port Arbitration Table Port Arbitration Table Port Arbitration Table Port Arbitration Table ...

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... Capability List Register Device Capabilities Register Device Status Register/Device Control Register Link Capabilities Register Link Status Register/Link Control Register Slot Capabilities Register Slot Status Register/ Slot Control Register Root Control Register Root Status Register Chapter 6: Register Descriptions December 2010 Altera Corporation ...

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... VC Resource Control Register (7) 0x16C VC Resource Status Register (7) ReservedP Table 6-10. PCI Express Advanced Error Reporting Extended Capability Structure, Rev2 Spec: Advanced Error Reporting December 2010 Altera Corporation Corresponding Section in PCIe Specification Capability List Register PCI Express Capabilities Register /PCI Express Capability List Register ...

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... Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register Root Error Command Register Root Error Status Register Error Source Identification Register Chapter 6: Register Descriptions December 2010 Altera Corporation ...

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... Signals—Hard IP Implementation” on page Implementation” on page Reset Hard IP Implementation Altera provides two options for reset circuitry in the PCI Express hard IP implementation using the MegaWizard Plug-In Manager. Both options are automatically created when you generate your IP core. These options are implemented by following files: ■ ...

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... ALTGXB_Reconfig altpcie_reconfig_ <device>.v or .vhd locked PLL altpcierd_reconfig_pll_clk.v Chapter 7: Reset and Clocks Reset Hard IP Implementation Transceiver PHY IP Core <variant>_serdes.v or .vhd or .vhd Refclk 100 MHz cal_blk_clk 50 MHz reconfig_clk 50 MHz fixedclk 125 MHz Reset Control and Power Down December 2010 Altera Corporation ...

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... You can use the reset sequence provided for the hard IP implementation in the <variant>_rs_hip.v or .vhd IP core as a reference in designing your own circuit. In addition, to understand the domain of each reset signal, refer to Domains, Hard IP and ×1 and ×4 Soft IP Implementations” on page December 2010 Altera Corporation Figure 7–1. Hip_txclk 125 or 250 MHz ...

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... Note (1) srst crst npor SERDES Reset Controller pll_locked rx_pll_locked <variant> _serdes.v or .vhd tx_digitalreset rx_analogreset rx_digitalreset pll_powerdown gxb_powerdown Note (3) Note (4) Chapter 7: Reset and Clocks Reset in Stratix V Devices l2_exit hotrst_exit Note (2) dlup_exit dl_ltssm[4:0] tx_digitalreset rx_analogreset rx_digitalreset rx_freqlocked pll_locked rx_pll_locked December 2010 Altera Corporation ...

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... This section discusses the domain of each of the reset signal in the <variant>.v or .vhd IP core. The hard IP implementation (×1, ×4, and ×8) or the soft IP implementation (×1 and ×4) have the following three reset inputs: December 2010 Altera Corporation Specification. The PCI Express IP core has several reset 5–24. <variant>_plus .v or .vhd < ...

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... PCI Express Compiler User Guide <variant> .vhd <variant> _core.v or .vhd altpcie_hip_pipen1b.v or .vhd npor SERDES Reset State Machine Configuration Space Sticky Registers Configuration Space crst Non-Sticky Registers srst Datapath State Machines of MegaCore Fucntion Chapter 7: Reset and Clocks Reset in Stratix V Devices December 2010 Altera Corporation ...

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... The user application interface is synchronous to the pld_clk input. December 2010 Altera Corporation 7–7 PCI Express Compiler User Guide ...

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... MHz - x8 cal_blk_clk reconfig_clk fixedclk tx_clk_out <variant>_core.v or .vhd (PCIe MegaCore Function) Transceiver Architecture in Volume II of the Arria II Device Handbook, Transceiver Architecture in Volume 2 of the Stratix IV Device Handbook, or Chapter 7: Reset and Clocks Clocks Application Clock Transceivers Altera PHY IP User December 2010 Altera Corporation ...

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... Gen2. The PCI Express specification allows a +/- 300 ppm variation on the clock frequency. The CDC module implements the asynchronous clock domain crossing between the PHY/MAC p_clk domain and the data link layer core_clk domain. December 2010 Altera Corporation PCI Express Hard IP - Three Clock Domains Clock Data Link ...

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... MHz 125 MHz 62.5 MHz 62.5 MHz (1) 125 MHz 125 MHz 250 MHz 250 MHz 250 MHz 125 MHz 125 MHz 125 MHz 250 MHz 250 MHz 250 MHz 125 MHz 500 MHz 250 MHz December 2010 Altera Corporation ...

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... The clk125_out is driven by the output of the transceiver. The clk125_out must be connected back to the clk125_in input, possibly through a clock distribution circuit required by the specific application. The user application interface is synchronous to the clk125_in input. December 2010 Altera Corporation <variant> .vhd PLL refclk clk125_out ...

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... MegaCore Function) Transceivers in Volume 2 of the Stratix IV Device Handbook, or Chapter 7: Reset and Clocks Clocks clk62.5_out or clk125_out Application C Transceiver in Volume 2 of the Cyclone IV Device Altera PHY IP User Guide for December 2010 Altera Corporation ...

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... MegaCore Function) clk250_in Transceivers in Volume 2 of the Stratix IV Device Handbook, or 7–13 clk250_out Application Clock Transceiver in Volume 2 of the Cyclone IV Device Altera PHY IP User Guide for PCI Express Compiler User Guide ...

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... PCI Express Compiler User Guide <variant> .vhd - For Simulation PLL refclk clk125_out pll_inclk core_clk_out <variant> _core.v or .vhd (PCIe MegaCore Function) pld_clk Use separate clock option on the Avalon Configuration Settings Chapter 7: Reset and Clocks Clocks Application Clock Figure 7–12, December 2010 Altera Corporation ...

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... Avalon-MM global clock, AvlClk_L. If you turn on the make appropriate clock assignments for all Avalon-MM components. illustrates a system that uses a single clock domain. Figure 7–13. Connectivity for a PCI Express IP core with a Single Clock Domain December 2010 Altera Corporation Avalon clk clk MM ...

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... Builder and can be selected as the clock source for any Avalon-MM component in the system. In this clocking mode, the PCI Express IP core’s Avalon-MM logic operates on an external clock source while the IP core protocol layers operate on an internally generated clock. December 2010 Altera Corporation Chapter 7: Reset and Clocks Clocks ...

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... Receive Transmit Power Management Messages PM_Active_State_Nak Transmit Receive PM_PME Receive Transmit PME_Turn_Off Transmit Receive PME_TO_Ack Receive Transmit December 2010 Altera Corporation 8. Transaction Layer Protocol (TLP) (Note 1) Generated by Core App Core (with AL Layer input) For endpoints, only INTA messages are generated. No Yes No ...

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... No Yes No layer in the hard IP implementation. For soft IP implementation, following the PCI No Yes No Express Specification 1.0a, these messages are No Yes No transmitted to the application layer. No Yes No Supported Message Types Comments (1) PCI Express , these December 2010 Altera Corporation ...

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... The transaction layer interprets requests using the 64-bit format for addresses below 4 GBytes as malformed packets and does not send them to the application layer. If the AER option is on, an error message TLP is sent to the root port. December 2010 Altera Corporation (Note 1) Generated by Core ...

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... Read Request Request Spec Core Spec Core yes yes yes yes Y/N 1) Yes Y/N 2) Yes Y/N 3) Yes Y/N 4) Yes Receive Buffer Reordering Completion I/O or Cfg Write Read Completion Completion Spec Core Spec Core Y/N No Y/N No Y/N No Y/N No December 2010 Altera Corporation ...

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... Read Completions for Request (same Transaction ID) must return in address order. 1 MSI requests are conveyed in exactly the same manner as PCI Express memory write requests and are indistinguishable from them in terms of flow control, ordering, and data integrity. December 2010 Altera Corporation (Note 1)– (12) Yes ...

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... PCI Express Compiler User Guide Chapter 8: Transaction Layer Protocol (TLP) Details Receive Buffer Reordering December 2010 Altera Corporation ...

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... ECRC. If the ECRC option is turned off, no error detection takes place. If the ECRC forwarding option is turned on, the ECRC value is forwarded to the application layer with the TLP. If ECRC forwarding option is turned off, the ECRC value is not forwarded. December 2010 Altera Corporation 9. Optional Features PCI Express Base Specification, Rev. 2.0. ...

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... TD=1, with ECRC TD=1, with ECRC TD=0, without ECRC TD=0, without ECRC Yes TD=1, with ECRC TD=1, with ECRC Chapter 9: Optional Features ECRC TLP Forward to Application “Capabilities (Note 1) TLP on Link Comments ECRC is generated Core forwards the ECRC December 2010 Altera Corporation ...

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... PHY device the L2 state, only auxiliary power is available; main power is off. Because the auxiliary power supply is insufficient to run an FPGA, Altera FPGAs provide pseudo-support for this state. The pm_auxpwr signal, which indicates that auxiliary power has been detected, can be hard-wired high. ...

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... L0s acceptable latency is 512 ns, software will probably not enable the entry to L0s for the endpoint. PCI Express Compiler User Guide Chapter 9: Optional Features Active State Power Management (ASPM) Table 9–3 describes the L0s and L1 exit Description December 2010 Altera Corporation ...

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... Some time adjustment may be necessary if one or more switches are located between the endpoint and the root port maximize performance, Altera recommends that you set L0s and L1 acceptable latency values to their minimum values. Lane Initialization and Reversal Connected PCI Express components need not support the same number of lanes. The × ...

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... Signals Route Easily PCI Express PCI Express Endpoint Root Port lane 1 2 reversal and 3 on page Chapter 9: Optional Features Instantiating Multiple PCI Express IP Cores PCI Express Endpoint 0 1 lane 2 reversal 3 16–7. After you display the clock December 2010 Altera Corporation ...

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... Source Multiple Tcl Scripts If you use Altera-provided Tcl scripts to specify constraints for IP cores, you must run the Tcl script associated with each generated PCI Express IP core. For example system has pcie1 and pcie2 IP core variations, and uses the pci_express_compiler.tcl constraints file, then you must source the constraints for both IP cores sequentially from the Tcl console after generation ...

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... PCI Express Compiler User Guide Chapter 9: Optional Features Instantiating Multiple PCI Express IP Cores December 2010 Altera Corporation ...

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... MSI posted write TLP to be generated based on the MSI configuration register values and the app_msi_tc and app_msi_num input ports. Figure 10–1 illustrates the architecture of the MSI handler block. Figure 10–1. MSI Handler Block December 2010 Altera Corporation PCI Express 2.0 Base Specification for a general description of PCI app_msi_req app_msi_ack ...

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... R/W app_int_sts1 Figure 10–3, the endpoint requests eight MSIs but is only Root Complex Root Endpoint Port 8 Requested 2 Allocated Interrupt Register Chapter 10: Interrupts MSI Interrupts app_int_sts msi_enable & Master Enable app_msi_req MSI app_msi_ack Arbitration CPU Interrupt Block December 2010 Altera Corporation ...

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... Figure 10–5 illustrates interrupt timing for the legacy interface. In this figure the assertion of app_int_ack indicates that the Assert_INTA message TLP has been sent. Figure 10–5. Legacy Interrupt Assertion app_int_sts app_int_ack December 2010 Altera Corporation clk PCI Local Bus Specification, Revision Figure 10–5 ...

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... The Root Error Status register reports the status of error messages. The root error status register is part of the PCI Express AER extended capability structure located at offset 0x830 of the configuration space registers. PCI Express Compiler User Guide clk MSI 29:0 Chapter 10: Interrupts PCI Express Interrupts for Root Ports Allocated 1:0 2:0 December 2010 Altera Corporation ...

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... Posted Data Non-Posted Headers ■ ■ Non-Posted Data ■ Completion Headers ■ Completion Data December 2010 Altera Corporation 11–2. This section discusses the Flow Control 11–1. If the requester of the writes sources the data as quickly as 11. Flow Control PCI Express Compiler User Guide ...

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... Physical Data Link Express Layer Layer Layer Link Figure 11–1 show the general area to which they Chapter 11: Flow Control Throughput of Posted Writes FC Update Credit DLLP Allocated Incr Data Packet Buffer Transaction App Layer Layer Layer Data Sink December 2010 Altera Corporation ...

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... From PCI Express Link until packet is available at Application Layer interface. From Application Layer draining packet to generation and transmission of Flow Control (FC) Update DLLP on PCI Express Link (assuming no arbitration delay). December 2010 Altera Corporation PCI Express Base Specification ×8 Function ×4 Function Min Max ...

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... Chapter 11: Flow Control Throughput of Non-Posted Reads (Note 1), (Note 2) ×4 Function ×1 Function Min Max Min Max 184 232 424 472 ×1 Function Max Min Max 128 96 96 192 192 192 384 384 384 December 2010 Altera Corporation ...

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... You can adjust the Desired performance for received completions up or down from the High setting to tailor the RX buffer size to your delays and required performance. December 2010 Altera Corporation 11–1. The paths for the read requests and the ×8 Function × ...

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... For the ×1 and ×4 functions, you can specify up to 256 tags, though configuration software can restrict the application to use only 32 tags. In commercial PC systems, 32 tags are typically sufficient to maintain optimal read throughput. PCI Express Compiler User Guide Chapter 11: Flow Control Throughput of Non-Posted Reads December 2010 Altera Corporation ...