IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 198

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

11–4
Table 11–1. FC Update Loop Delay in Nanoseconds Components For Stratix II GX (Part 2 of 2)
Table 11–2. Data Credits Required By Packet Size
Throughput of Non-Posted Reads
PCI Express Compiler User Guide
From receipt of FC Update DLLP on the PCI
Express Link to updating of transmitter's Credit
Limit register.
Note to
(1) The numbers for other Gen1 PHYs are similar.
(2) Gen2 numbers are to be determined.
Table
Max Packet Size
11–1:
1024
2048
128
256
512
Delay Path
Based on the above FC Update Loop delays and additional arbitration and packet
length delays,
advertised to cover the delay. The RX buffer size must support this number of credits
to maintain full bandwidth.
These numbers take into account the device delays at both ends of the PCI Express
link. Different devices at the other end of the link could have smaller or larger delays,
which affects the minimum number of credits required. In addition, if the application
layer cannot drain received packets immediately in all cases, it may be necessary to
offer additional credits to cover this delay.
Setting the Desired performance for received requests to High on the Buffer Setup
page on the Parameter Settings tab using the parameter editor configures the RX
buffer with enough space to meet the above required credits. You can adjust the
Desired performance for received request up or down from the High setting to tailor
the RX buffer size to your delays and required performance.
To support a high throughput for read data, you must analyze the overall delay from
the time the application layer issues the read request until all of the completion data is
returned. The application must be able to issue enough read requests, and the read
completer must be capable of processing these read requests quickly enough (or at
least offering enough non-posted header credits) to cover this delay.
However, much of the delay encountered in this loop is well outside the PCI Express
IP core and is very difficult to estimate. PCI Express switches can be inserted in this
loop, which makes determining a bound on the delay more difficult.
Min
128
192
384
64
80
Table 11–2
×8 Function
shows the number of flow control credits that must be
Max
112
160
256
384
96
Min
116
×8 Function
Max
160
Min
128
192
384
56
80
×4 Function
Min
184
×4 Function
Max
128
192
384
80
96
Max
232
December 2010 Altera Corporation
Throughput of Non-Posted Reads
(Note
Min
192
384
40
64
96
Chapter 11: Flow Control
×1 Function
1),
Min
424
×1 Function
(Note 2)
Max
192
384
48
64
96
Max
472