IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 95

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Figure 5–9. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-DWord Header TLPs with Non-QWord Addresses
Note to
(1) rx_st_be[7:4] corresponds to rx_st_data[63:32]. rx_st_be[3:0] corresponds to rx_st_data[31:0].
Figure 5–10. 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-DWord Header TLPs with QWord Aligned Addresses
December 2010 Altera Corporation
(Note 1)
Figure
rx_st_data[127:96]
rx_st_data[63:32]
rx_st_bardec[7:0]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_bardec[7:0]
rx_st_data[31:0]
rx_st_data[31:0]
5–9:
rx_st_be[7:4]
rx_st_be[3:0]
rx_st_empty
rx_st_valid
rx_st_eop
rx_st_sop
rx_st_eop
rx_st_sop
clk
clk
Figure 5–9
for a four dword header with non-qword addresses with a 64-bit bus. Note that the
address of the first dword is 0x4. The address of the first enabled byte is 0x6. This
example shows one valid word in the first dword, as indicated by the rx_st_be signal.
Figure 5–10
for TLPs with a three dword header and qword aligned addresses.
header1
header0
shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs
shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs
header2
header1
header0
01
header3
header2
10
data3
data2
data1
data0
data0
C
data<n-1>
data<n>
data2
data1
F
F
PCI Express Compiler User Guide
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