IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 309

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
December 2010 Altera Corporation
Receive Datapath Interface Signals
1
In
channel, while configuration and global signals are common to all virtual channels on
a link.
Table B–1
each interface.
Table B–1. Signal Groups in the PCI Express IP core using the Descriptor/Data Interface
The receive interface, like the transmit interface, is based on two independent buses:
one for the descriptor phase (rx_desc[135:0]) and one for the data phase
(rx_data[63:0]). Every transaction includes a descriptor. A descriptor is a standard
transaction layer packet header as defined by the
or 2.0
group and bits 135:128 describe BAR and address decoding information (refer to
rx_desc[135:0] in
Receive datapath signals can be divided into the following two groups:
■
■
In the following tables, transmit interface signal names with a <n> suffix are for
virtual channel <n>. If the IP core implements multiple virtual channels, there are an
additional sets of signals for each virtual channel number.
Signal Group
Descriptor RX
Descriptor TX
Clock
Reset
Interrupt
Configuration space
Power management
Completion
Transceiver Control
Serial
Pipe
Test
Figure
Descriptor phase signals
Data phase signals
with two exceptions. Bits 126 and 127 indicate the transaction layer packet
B–2, the transmit and receive signals apply to each implemented virtual
lists the interfaces for this MegaCore with links to the sections that describe
Table B–2
“Receive Datapath Interface Signals” on page B–3
“Transmit Operation Interface Signals” on page B–12
“Clock Signals—Soft IP Implementation” on page 5–23
“Reset and Link Training Signals” on page 5–24
“PCI Express Interrupts for Endpoints” on page 5–29
“Configuration Space Signals—Soft IP Implementation” on page 5–39
“PCI Express Reconfiguration Block Signals—Hard IP Implementation”
on page 5–41
“Completion Interface Signals for Descriptor/Data Interface” on
page B–25
“Transceiver Control” on page 5–53
“Serial Interface Signals” on page 5–55
“PIPE Interface Signals” on page 5–56
“Test Interface Signals—Soft IP Implementation” on page 5–60
for details).
Physical
Logical
Test
PCI Express Base Specification 1.0a, 1.1
Description
PCI Express Compiler User Guide
B–3