IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 180

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

8–4
Receive Buffer Reordering
Table 8–2. Transaction Ordering Rules (Part 1 of 2)
PCI Express Compiler User Guide
Row Pass Column
Memory Write or
Message
Request
Read Request
I/O or
Configuration
Write Request
■
■
The receive datapath implements a receive buffer reordering function that allows
posted and completion transactions to pass non-posted transactions (as allowed by
PCI Express ordering rules) when the application layer is unable to accept additional
non-posted transactions.
The application layer dynamically enables the RX buffer reordering by asserting the
rx_mask signal. The rx_mask signal masks non-posted request transactions made to
the application interface so that only posted and completion transactions are
presented to the application.
Spec
1) N
2)Y/N
No
No
Memory Write or
Posted Request
The transaction layer sends all memory and I/O requests, as well as completions
generated by the application layer and passed to the transmit interface, to the PCI
Express link.
The IP core can generate and transmit power management, interrupt, and error
signaling messages automatically under the control of dedicated signals.
Additionally, the IP core can generate MSI requests under the control of the
dedicated signals.
Message
Request
Core
1) N
2) N
No
No
Spec
yes
Y/N
Y/N
Read Request
Non Posted Request
(Note
Core
yes
1) Yes
3) Yes
Table 8–2
1)–
(12)
Spec
yes
Y/N
Y/N
I/O or Cfg Write
lists the transaction ordering rules.
Request
Core
yes
2) Yes
4) Yes
Chapter 8: Transaction Layer Protocol (TLP) Details
Y/N
Read Completion
Spec
1) Y/N
2) Y
Y/N
December 2010 Altera Corporation
Core
1) N
2) N
No
No
Completion
Receive Buffer Reordering
Spec
1) Y/N
2) Y
Y/N
Y/N
I/O or Cfg Write
Completion
Core
1) No
2) No
No
No