IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 136

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–52
Table 5–29. Avalon-MM Reset and Status Signals
Figure 5–42. PCI Express SOPC Builder Reset Diagram
Note to figure
(1) The system-wide reset, reset_n indirectly resets all PCI Express IP core circuitry not affected by PCIe_rstn using the Reset_n_pcie signal
(2) For a description of the dl_ltssm[4:0] bus, refer to
PCI Express Compiler User Guide
pcie_rstn
reset_n
suc_spd_neg
and the Reset Synchronizer module.
Reset and Status Signals
Signal
Reset_n
Table 5–29
in SOPC Builder.
Figure 5–42
Pcie_rstn also resets the rest of the PCI Express IP core, but only after the following
synchronization process:
1. When Pcie_rstn asserts, the reset request module asserts reset_request,
2. The Reset Synchronizer block sends a reset pulse, Reset_n_pcie, synchronized to
synchronized to the Avalon-MM clock, to the Reset Synchronizer block.
the Avalon-MM clock, to the PCI Express Compiler IP core.
Reset_request
Reset_n_pcie
I/O
O
I
I
Reset Request
Module
Pcie_rstn directly resets all sticky PCI Express IP core configuration registers through
the npor input. Sticky registers are those registers that fail to reset in L2 low power
mode or upon a fundamental reset.
reset_n is the system-wide reset which resets all PCI Express IP core circuitry not
affected by pcie_rstn/pcie_rstn_export.
suc_spd_neg is a status signal which Indicates successful speed negotiation to Gen2
when asserted.
describes the reset and status signals for the PCI Express IP cores generated
shows the PCI Express reset logic for SOPC Builder.
PCI Express MegaCore Function
PCIe_rstn
Table
RxmResetRequest_o
5–7.
(to PCI Express Clock)
Reset Synchronizer
Description
npor
srst
crst
Rstn_i
npor
l2_exit
hotrst_exit
dlup_exit
dl_ltssm[4:0]
Avalon-MM Bridge
Transaction Layer
Data Link Layer
Physical Layer
PCI Express
December 2010 Altera Corporation
Avalon-MM Application Interface
Chapter 5: IP Core Interfaces