IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 88

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–4
Figure 5–3. Signals in the Soft IP Implementation with Avalon-ST Interface
Notes to
(1) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. The reconfig_fromgxb is a single wire for Stratix II GX and
(2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> = 2. For
PCI Express Compiler User Guide
(Path to
Virtual
Channel 0)
Rx Port
Arria GX. For Stratix IV GX, <n> = 16 for ×1 and ×4 IP cores and <n> = 33 the ×8 IP core.
Stratix IV GX, <n> = 3.
Figure
Component
Avalon-ST
Component
Interrupt
Completion
Interface
Avalon-ST
Specific
Power
Mnmt
5–3:
Specific
Config
Reset
Clock
tx_st_ready0
tx_st_valid0
tx_st_data0[63:0]
tx_st_sop0
tx_st_eop0
tx_st_err0
tx_cred0[35..0]
tx_fifo_empty0
tx_fifo_rdptr0[3:0]
tx_fifo_wrptr0[3:0]
tx_fifo_full0
refclk
clk250_in - x8
clk250_out - x8
clk125_in - x1 and x4
clk125_out - x1 and x4
npor
srst - x1 and x4
crst - x1 and x4
rstn - x8
l2_exit
hotrst_exit
dlup_exit
dl_ltssm[4:0]
app_msi_req
app_msi_ack
app_msi_tc [2:0]
app_msi_num [4:0]
pex_msi_num [4:0]
app_int_sts
app_int_ack - x1 and x4
pme_to_cr
pme_to_sr
cfg_pmcsr[31:0]
cfg_tcvcmap [23:0]
cfg_busdev [12:0]
cfg_prmcsr [31:0]
cfg_devcsr [31:0]
cfg_linkcsr [31:0]
cfg_msicsr [15:0]
cpl_err[6:0]
cpl_pending
err_desc_func0 [127:0]- x1, x4
rx_st_ready0
rx_st_valid0
rx_st_data0[63:0]
rx_st_sop0
rx_st_eop0
rx_st_err0
rx_st_mask0
rx_st_bardec0[7:0]
rx_st_be0[7:0]
PCI Express Soft IP Core
×1 and ×4 only
(1)
(2)
reconfig_fromgxb[ <n> :0]
powerdown_ext[1:0]
powerdown_ext[1:0]
reconfig_togxb[ <n> :0]
rxstatus0_ext[2:0]
rxstatus0_ext[2:0]
tx_st_fifo_empty0
rxdata0_ext[15:0]
txdata0_ext[15:0]
rxdatak0_ext[1:0]
txdatak0_ext[1:0]
rxdata0_ext[7:0]
xphy_pll_locked
txdata0_ext[7:0]
xphy_pll_areset
gxb_powerdown
rxelecidle0_ext
rxelecidle0_ext
( user specified,
txelecidle0_ext
txelecidle0_ext
test_out[511:0]
rxpolarity0_ext
rxpolarity0_ext
tx_st_fifo_full0
up to 512 bits)
txdetectrx_ext
txdetectrx_ext
phystatus_ext
phystatus_ext
txcompl0_ext
txcompl0_ext
txdatak0_ext
rxdatak0_ext
test_in[31:0]
rxvalid0_ext
rxvalid0_ext
reconfig_clk
pipe_mode
cal_blk_clk
pipe_txclk
pipe_rstn
rate_ext
tx_out0
tx_out1
tx_out2
tx_out3
tx_out4
tx_out5
tx_out6
tx_out7
rx_in0
rx_in1
rx_in2
rx_in3
rx_in4
rx_in5
rx_in6
rx_in7
for x8
and x4
8-bit
PIPE
16-bit
for x1
Transceiver
PIPE
Test
Interface
December 2010 Altera Corporation
internal
Serial
Control
IF to
PIPE
PHY
for
Chapter 5: IP Core Interfaces
x4 MegaCore
x8 MegaCore
Repeated for
Repeated for
Lanes 1-3 in
Lanes 1-7 in
Avalon-ST Interface
external
PHY
for