IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 84

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–26
PCI Express Compiler User Guide
Avalon-MM RX Master Block
PCI Express TX Block
Interrupt Handler Block
f
1
The RX block passes header information to Avalon-MM master which generates the
corresponding transaction to the Avalon-MM interface. Additional requests from the
PCI Express IP core are not accepted while a request is being processed. For reads, the
RX block deasserts the ready signal until the corresponding completion packet is sent
to the PCI Express IP core via the PCIe TX block. For writes, requests must be sent to
the Avalon-MM system interconnect fabric before the next request is accepted.
The 32-bit Avalon-MM master connects to the Avalon-MM system interconnect fabric.
It drives read and write requests to the connected Avalon-MM slaves, performing the
required address translation. The RX master supports all legal combinations of byte
enables for both read and write requests.
For more information about legal combinations of byte enables, refer to Chapter 3,
Avalon Memory-Mapped Interfaces in the
The PCI Express TX Completion block sends completion information to the PCI
Express IP core. The IP core then sends this information to the root complex. The TX
completion block generates a completion packet with Completer Abort (CA) status
and no completion data for unsupported requests. The TX completion block also
supports the zero-length read (flush) command.
The interrupt handler implements both INTX and MSI interrupts. The msi_enable bit
in the configuration register specifies the interrupt type. The msi_enable_bit is part
of MSI message control portion in MSI Capability structure. It is bit[16] of 0x050 in the
configuration space registers. If the msi_enable bit is on, an MSI request is sent to the
PCI Express IP core when received, otherwise INTX is signaled. The interrupt handler
block supports a single interrupt source, so that software may assume the source. You
can disable interrupts by leaving the interrupt signal unconnected in the IRQ column
of SOPC Builder.
When the MSI registers in the configuration space of the completer only single dword
PCI Express IP core are updated, there is a delay before this information is propagated
to the Bridge module shown in
module to update the MSI register information. Under normal operation,
initialization of the MSI registers should occur substantially before any interrupt is
generated. However, failure to wait until the update completes may result in any of
the following behaviors:
■
■
■
Sending a legacy interrupt instead of an MSI interrupt
Sending an MSI interrupt instead of a legacy interrupt
Loss of an interrupt request
Figure
4–14. You must allow time for the Bridge
Avalon Interface Specifications.
Completer Only PCI Express Endpoint Single DWord
December 2010 Altera Corporation
Chapter 4: IP Core Architecture