IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 211

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 13: Reconfiguration and Offset Cancellation
Dynamic Reconfiguration
Table 13–1. Dynamically Reconfigurable Registers in the Hard IP Implementation (Part 4 of 7)
December 2010 Altera Corporation
0x96
Address
Bits
13:11
3:0
7:5 Reserved.
3:1 Interrupt pin.
5:4 Reserved.
10
14
15 MSI per-bit vector masking (read-only field).
4
8 ECRC generate.
9 ECRC check.
0 Function supports MSI.
6 Function supports MSI-X.
Completion timeout ranges. The following encodings are
defined:
Completion Timeout supported
No command completed support. (available only in PCI
Express Base Specification Revision 1.1 compliant Cores)
Number of functions MSI capable.
MSI 32/64-bit addressing mode.
b’0001: range A.
b’0010: range B.
b’0011: range A&B.
b’0110: range B&C.
b’0111: range A,B&C.
b’1110: range B,C&D.
b’1111: range A,B,C&D.
All other values are reserved.
0: completion timeout disable not supported
1: completion timeout disable supported
b’000: 1 MSI capable.
b’001: 2 MSI capable.
b’010: 4 MSI capable.
b’011: 8 MSI capable.
b’100: 16 MSI capable.
b’101: 32 MSI capable.
b’0: 32 bits only.
b’1: 32 or 64 bits
Description
Default
b’0000
Value
b’001
b’010
b’00
b’0
b’0
b’0
b’0
b’0
b’1
b’0
b’1
b’0
PCI Express Compiler User Guide
Table 6–8 on page
Device Capability
register 2
Table 6–8 on page
Device Capability
register 2
Table 6–10 on page
Advanced Error
Capability and Control
register
Table 6–10 on page
Advanced Error
Capability and Control
register
Table 6–8 on page
Slot Capability register
Table 6–4 on page
Message Control
register
Table 6–4 on page
Message Control
register for MSI
Table 6–4 on page
Message Control
register for MSI
Additional Information
—
—
6–5,
6–5,
6–5,
6–3,
6–3,
6–3,
6–6,
6–6,
13–5