IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 262

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–34
BFM Procedures and Functions
PCI Express Compiler User Guide
BFM Read and Write Procedures
1
1
■
These routines take as parameters a BAR number to access the memory space and the
BFM shared memory address of the bar_table data structure that was set up by the
ebfm_cfg_rp_ep procedure. (Refer to
page
access an offset from a specific BAR and eliminates calculating the addresses assigned
to the specified BAR.
The root port BFM does not support accesses to endpoint I/O space BARs.
For further details on these procedure calls, refer to the section
Procedures” on page
This section describes the interface to all of the BFM procedures, functions, and tasks
that the BFM driver uses to drive endpoint application testing.
The last subsection describes procedures that are specific to the chaining DMA design
example.
This section describes both VHDL procedures and functions and Verilog HDL
functions and tasks where applicable. Although most VHDL procedure are
implemented as Verilog HDL tasks, some VHDL procedures are implemented as
Verilog HDL functions rather than Verilog HDL tasks to allow these functions to be
called by other Verilog HDL functions. Unless explicitly specified otherwise, all
procedures in the following sections also are implemented as Verilog HDL tasks.
You can see some underlying Verilog HDL procedures and functions that are called by
other procedures that normally are hidden in the VHDL package. You should not call
these undocumented procedures.
This section describes the procedures used to read and write data among BFM shared
memory, endpoint BARs, and specified configuration registers.
The following procedures and functions are available in the VHDL package
altpcietb_bfm_rdwr.vhd or in the Verilog HDL include file altpcietb_bfm_rdwr.v.
These procedures and functions support issuing memory and configuration
transactions on the PCI Express link.
All VHDL arguments are subtype natural and are input-only unless specified
otherwise. All Verilog HDL arguments are type integer and are input-only unless
specified otherwise.
ebfm_barrd_nowt—reads data from an offset of a specific endpoint BAR and stores
it in the BFM shared memory. This procedure returns as soon as the request has
been passed to the VC interface module for transmission, allowing subsequent
reads to be issued in the interim.
15–28.) Using these parameters simplifies the BFM test driver routines that
15–34.
“Configuration of Root Port and Endpoint” on
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
“BFM Read and Write
BFM Procedures and Functions