IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 337

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Incremental Compile Module for Descriptor/Data Examples
Table B–13. ICM Files
December 2010 Altera Corporation
altpcierd_icm_top.v or
altpcierd_icm_top.vhd
altpcierd_icm_rx.v or
altpcierd_icm_rx.vhd
altpcierd_icm_rxbridge.v or
altpcierd_icm_rxbridge.vhd
altpcierd_icm_tx.v or
altpcierd_icm_tx.vhd
altpcierd_icm_msibridge.v or
altpcierd_icm_msibridge.vhd
altpcierd_icm_txbridge_withbypass.v or
altpcierd_icm_txbridge_withbypass.vhd
altpcierd_icm_txbridge.v or
altpcierd_icm_txbridge.vhd
altpcierd_icm_tx_pktordering.v or
altpcierd_icm_tx_pktordering.vhd
altpcierd_icm_npbypassctl.v or
altpcierd_icm_npbypassctl.vhd
altpcierd_icm_sideband.v or
altpcierd_icm_sideband.vhd
altpcierd_icm_fifo.v or
altpcierd_icm_fifo.vhd
altpcierd_icm_fifo_lkahd.v or
altpcierd_icm_fifo_lkahd.vhd
altpcierd_icm_defines.v or
altpcierd_icm_defines.vhd
Filename
When using the Quartus II software, include the files listed in
design:
ICM Application-Side Interface
Tables and timing diagrams in this section describe the following application-side
interfaces of the ICM:
■
■
■
■
RX ports
TX ports
MSI port
Sideband interface
This is the top-level module for the ICM instance. It contains all of the following
modules listed below in column 1.
This module contains the ICM RX datapath. It instantiates the
altpcierd_icm_rxbridge and an interface FIFO.
This module implements the bridging required to connect the application’s
interface to the PCI Express transaction layer.
This module contains the ICM TX and MSI datapaths. It instantiates the
altpcierd_icm_msibridge, altpcierd_icm_txbridge_withbypass, and interface
FIFOs.
This module implements the bridging required to connect the application’s
Avalon-ST MSI interface to the PCI Express transaction layer.
This module instantiates the altpcierd_icm_txbridge and
altpcierd_icm_tx_pktordering modules.
This module implements the bridging required to connect the application’s
Avalon-ST TX interface to the IP core’s TX interface.
This module contains the NP-Bypass function. It instantiates the npbypass FIFO
and altpcierd_icm_npbypassctl.
This module controls whether a Non-Posted PCI Express request is forwarded
to the IP core or held in a bypass FIFO until the IP core has enough credits to
accept it. Arbitration is based on the available non-posted header and data
credits indicated by the IP core.
This module implements incremental-compile boundary registers for the
non-timing critical sideband signals to and from the IP core.
This is a MegaWizard-generated RAM-based FIFO.
This is a MegaWizard-generated RAM-based look-ahead FIFO.
This file contains global define’s used by the Verilog ICM modules.
Description
PCI Express Compiler User Guide
Table B–13
in your
B–31