IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 173

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Reset and Clocks
Clocks
December 2010 Altera Corporation
Refer to
Figure 7–10. Stratix II GX ×8 with 100 MHz Reference Clock
Note to
(1) Different device families require different frequency ranges for the calibration and reconfiguration clocks. To
(2) You must provide divide-by-two logic to create a 125 MHz clock source for fixedclk.
Clock Source
Clock Source
Clock Source
determine the frequency range for your device, refer to one of the following device handbooks:
Architecture
Handbook,
Stratix V devices.
Calibration
100-MHz
Reconfig
Note (1)
Figure
Figure 7–10
7–10:
Transceiver Architecture
in Volume II of the Arria II Device Handbook,
refclk
for this clocking configuration.
<variant> .v or .vhd
refclk
clk250_in
in Volume 2 of the Stratix IV Device Handbook, or
<variant> _serdes.v or .vhd
rx_cruclk
pll_inclk
cal_blk_clk
reconfig_clk
fixed_clk
(PCIe MegaCore Function)
<variant> _core.v or .vhd
(ALTGX or ALT2GX
Megafunction)
core_clk_out
Transceivers
in Volume 2 of the Cyclone IV Device
clk250_out
PCI Express Compiler User Guide
Altera PHY IP User Guide
Application Clock
Transceiver
7–13
for