IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 137

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Physical Layer Interface Signals
Table 5–30. Transceiver Control Signals (Part 1 of 2)
December 2010 Altera Corporation
cal_blk_clk
gxb_powerdown
Signal SOPC Builder
Transceiver Control
3. The Reset Synchronizer resynchronizes Reset_n_pcie to the PCI Express clock to
4. The reset_request signal deasserts after Reset_n_pcie asserts.
The system-wide reset, reset_n, resets all PCI Express IP core circuitry not affected by
Pcie_rstn. However, the reset logic first intercepts the asynchronous reset_n,
synchronizes it to the Avalon-MM clock, and sends a reset pulse, Reset_n_pcie to the
PCI Express Compiler IP core. The Reset Synchronizer resynchronizes Reset_n_pcie
to the PCI Express clock to reset the PCI Express Avalon-MM bridge as well as the
three PCI Express layers with srst and crst.
This section describes the global PHY support signals which are only present on
Arria GX, Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix II GX, Stratix IV GX
or Stratix V GX devices that use an integrated PHY. When selecting an integrated
PHY, the MegaWizard Plug-In Manager generates a SERDES variation file,
<variation>_serdes.<v or vhd >, in addition of the IP core variation file, <variation>.<v
or vhd>. For Stratix V GX devcies the SERDES entity is included in the PCI Express
compiler library files.
Table 5–30
reset the PCI Express Avalon-MM bridge as well as the three PCI Express layers
with srst and crst.
describes the transceiver support signals.
I/O
I
I
The cal_blk_clk input signal is connected to the transceiver calibration block
clock (cal_blk_clk) input. All instances of transceivers in the same device
must have their cal_blk_clk inputs connected to the same signal because
there is only one calibration block per device. This input should be connected to a
clock operating as recommended by the
Guide, the
Architecture
“Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix IV GX, Stratix V GX ×1, ×4,
or ×8 100 MHz Reference Clock” on page
IV GX PHY ×1 and ×4 and Arria II GX ×1, ×4, and ×8 with 100 MHz Reference
Clock” on page
page
The gxb_powerdown signal connects to the transceiver calibration block
gxb_powerdown input. This input should be connected as recommended by the
Stratix II GX Device Handbook
When the calibration clock is not used, this input must be tied to ground.
7–13.
Stratix IV Transceiver
in volume 2 of the Arria II GX Device Handbook. It is also shown in
7–12, and
“Stratix II GX ×8 with 100 MHz Reference Clock” on
or volume 2 of the
Architecture, or the
Description
The Stratix II GX Transceiver User
7–8,
“Arria GX, Stratix II GX, or Stratix
Stratix IV Device Handbook.
Arria II GX Transceiver
PCI Express Compiler User Guide
5–53