IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 29

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Parameterize the PCI Express
Figure 2–2. BAR Settings
Note to
(1) The endpoint chaining DMA design example DMA controller requires the use of BAR2 or BAR3.
December 2010 Altera Corporation
Figure
2–2:
10. Click Next to display the PCI Registers page. To enable all of the tests in the
Table 2–2. PCI Registers (Part 1 of 2)
PCI Base Registers (Type 0 Configuration Space)
Device ID
Subsystem ID
Revision ID
provided testbench and chaining DMA example design, make the base address
register (BAR) assignments shown in
Table
Register Name
2–2. provides the BAR assignments in tabular format.
BAR
0
1
2
32-Bit Non-Prefetchable Memory
32-Bit Non-Prefetchable Memory
32-bit Non-Prefetchable Memory
PCI Read-Only Registers
BAR TYPE
0xE001
0x2801
Value
0x01
Figure
2–2. Bar2 or Bar3 is required.
256 MBytes - 28 bits
PCI Express Compiler User Guide
256 KBytes - 18 bits
256 KBytes -18 bits
BAR Size
2–3