IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet
IPR-PCI/MT32
Specifications of IPR-PCI/MT32
Related parts for IPR-PCI/MT32
IPR-PCI/MT32 Summary of contents
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... Innovation Drive San Jose, CA 95134 www.altera.com PCI Compiler User Guide Compiler Version: Document Date: January 2011 10.1 ...
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... PCI Compiler User Guide Version 10.1 Altera Corporation ...
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... Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U ...
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... PCI Compiler User Guide Version 10.1 Altera Corporation ...
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... Create a New Quartus II Project .................................................................................................... 1–2 Launch IP Toolbench ....................................................................................................................... 1–4 Step 1: Parameterize ......................................................................................................................... 1–5 Step 2: Set Up Simulation ................................................................................................................ 1–7 Step 3: Generate ................................................................................................................................ 1–7 Simulate the Design ............................................................................................................................... 1–9 Simulation in the Quartus II Software ........................................................................................ 1–11 The Quartus II Simulation Files ......................................................................................................... 1–12 Master Simulation Files ................................................................................................................. 1–13 Target Simulation Files .................................................................................................................. 1–15 Altera Corporation Contents v ...
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... Header Type Register .................................................................................................................... 3–36 Base Address Registers .................................................................................................................. 3–37 CardBus CIS Pointer Register ....................................................................................................... 3–40 Subsystem Vendor ID Register .................................................................................................... 3–40 Subsystem ID Register ................................................................................................................... 3–41 Expansion ROM Base Address Register ..................................................................................... 3–41 Capabilities Pointer ........................................................................................................................ 3–42 Interrupt Line Register .................................................................................................................. 3–43 vi PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation ...
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... Target Mode Operation ............................................................................................................... 3–131 64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction ................................ 3–132 Master Mode Operation .............................................................................................................. 3–134 64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction ............................ 3–134 Chapter 4. Testbench General Description ............................................................................................................................... 4–1 Altera Corporation PCI Compiler Version 10.1 vii PCI Compiler User Guide ...
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... Program a Device ................................................................................................................................ 5–14 Upgrading Systems from a Previous Version ................................................................................. 5–15 Chapter 6. Parameter Settings System Options-1 ................................................................................................................................... 6–1 PCI Device Mode ........................................................................................................................ 6–1 PCI Target Performance ............................................................................................................. 6–3 PCI Master Performance ............................................................................................................ 6–5 Value of Multiple Pending Reads ....................................................................................................... 6–6 viii PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation ...
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... Avalon-To-PCI Read & Write Operation .................................................................................... 7–28 Avalon-to-PCI Write Requests ................................................................................................ 7–31 Avalon-to-PCI Read Requests ................................................................................................. 7–32 Arbitration Among Pending PCI Master Requests .............................................................. 7–34 Avalon-to-PCI Address Translation ............................................................................................ 7–35 Ordering of Requests ..................................................................................................................... 7–38 Ordering of Avalon-to-PCI Operations ................................................................................. 7–39 Altera Corporation PCI Compiler Version 10.1 ix PCI Compiler User Guide ...
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... Contents Ordering PCI-to-Avalon Operations ...................................................................................... 7–42 PCI Host-Bridge Operation ................................................................................................................ 7–45 Altera-Provided PCI Bus Arbiter ...................................................................................................... 7–45 Interrupts .............................................................................................................................................. 7–46 Generation of PCI Interrupts ................................................................................................... 7–46 Reception of PCI Interrupts ..................................................................................................... 7–46 Generation of Avalon-MM Interrupts ................................................................................... 7–47 Control & Status Registers ................................................................................................................. 7–47 PCI Interrupt Status Register ........................................................................................................ 7–49 PCI Interrupt Enable Register ...................................................................................................... 7–51 PCI Mailbox Register Access ........................................................................................................ 7– ...
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... A–6 Upgrading Assignments from a Previous Version of PCI Compiler ............................................ A–6 Upgrading PCI Assignments Containing Nondefault PCI Pin Names .................................. A–7 Additional Information Revision History ............................................................................................................................... Info–i How to Contact Altera .................................................................................................................... Info–ii Typographic Conventions ............................................................................................................. Info–iii Altera Corporation PCI Compiler Version 10.1 xi PCI Compiler User Guide ...
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... Contents xii PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation ...
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... PCI Compiler to meet your system requirements. The PCI Compiler contains the pci_mt64, pci_mt32, pci_t64, and pci_t32 MegaCore reference designs. Altera also offers the following development kits as PCI hardware prototyping platforms: ■ ■ ...
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... Table 1. PCI Compiler PCI Compiler Release Information Version Release Date Ordering Codes Product IDs Vendor ID Device Family The MegaCore functions provide either final or preliminary support for target Altera device families: Support ■ ■ ■ ■ 2 PCI Compiler User Guide provides information about this release of the PCI Compiler. ...
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... Table 2 functions for each Altera device family. Table 2. Device Family Support Arria Arria II GX Cyclone Cyclone II Cyclone III Cyclone III LS Cyclone IV GX HardCopy II HardCopy III HardCopy IV (E, GX) MAX Stratix Stratix GX Stratix II Stratix II GX Stratix III Stratix IV (E, GX) Other device families Note to ...
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... Dynamically negotiates 64-bit transactions and automatically ● multiplexes data on the local 64-bit data bus SOPC Builder ready PCI complexities, such as retry and disconnect are handled by the PCI/Avalon Bridge logic and transparent to the user PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Altera's devices, provides ample resources for custom local logic to accompany the PCI interface. The high performance of Altera's devices also enables these functions to support unlimited cycles of zero wait state memory-burst transactions. These functions can operate at either 33- or 66-MHz PCI bus clock speeds, ...
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... Design the DDR2 SDRAM controller interface. Specify the DDR2 SDRAM MegaCore function parameters. Design internal PCI and DDR2 SDRAM logic blocks. Write RTL code that connects the PCI and DDR2 SDRAM blocks. PCI Compiler Version 10.1 “Compliance Summary” Altera Corporation January 2011 ...
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... Figure 1 the PCI Compiler with MegaWizard Plug-in Manager flow; shaded areas represent user-customized blocks. Figure 1. PCI-to-DDR2 SDRAM Design Using the PCI Compiler With MegaWizard Flow Altera PCI MegaCore Function Local-Side, Low Level Interface Altera FPGA PCI Bus Altera PCI MegaCore Function ...
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... SOPC Builder graphical user interface (GUI). When comparing Figure option requires far less user customization. Figure 2. PCI-to-DDR2 SDRAM Design Using the PCI Compiler With SOPC Builder Flow Altera FPGA PCI Bus PCI Master/Target Component ...
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... Disadvantages ■ ■ Altera Corporation January 2011 summarizes the guidelines for selecting a particular flow over SOPC Builder Flow You would like to quickly integrate multiple system blocks. You are creating a new PCI design. You have limited PCI bus protocol experience ...
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... In addition to simulation, Altera performed extensive hardware testing on the functions to ensure robustness and PCI compliance. The test platforms include the Agilent E2928A PCI Bus Exerciser and Analyzer, an Altera PCI development board with a device configured with a PCI MegaCore function and a reference design, and PCI bus agents such ...
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... Ethernet network adapter, and video card. The Altera PCI MegaCore functions were tested on the Stratix EP1S25F1020C5 and EP1S60F1020C6 devices. Hardware testing ensures that the PCI MegaCore functions operate flawlessly under the most stringent conditions. During hardware testing with the Agilent E2928A PCI Bus Exerciser and Analyzer, various tests were performed to guarantee robustness and strict compliance ...
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... Stratix, Stratix GX, and Cyclone device families. This data was obtained by compiling each of the PCI MegaCore functions (parameterized to use one BAR that reserves 1 MByte of memory) in the Stratix EP1S60F1020C6 device. PCI Compiler Version 10.1 (1) f (MHz) I/O Pins MAX 89 > > > > (MHz) I/O Pins MAX 89 > > > > 67 Altera Corporation January 2011 ...
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... The speed and resource utilization estimates are for the supported devices when operating in the PCI Target-Only, PCI Master/Target, and PCI Host-Bridge device modes for each of the application-specific performance settings. 1 Altera Corporation January 2011 shows PCI MegaCore function resource utilization and Logic Elements (LEs) ...
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... PCI Compiler Version 10.1 (4) 64-Bit PCI Interface PCI M4K f MAX Memory I/O (MHz) Blocks Pins (3) 767 0 87 > > > >67 123 89 > > > > >67 Altera Corporation January 2011 ...
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... PCI Device PCI Target PCI Master Mode PCI Min N/A Target- Typical N/A Only Max N/A Altera Corporation January 2011 lists memory utilization and performance data for Cyclone II (1) 32-Bit PCI Interface Logic M4K I/O Elements Memory Pins (LEs) Blocks 547 ...
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... M512 Logic Memory I/O Elements Blocks Pins (LEs) (2) 3,668 10 89 4,187 14 89 4,682 14 89 5,138 16 89 5,634 20 89 6,696 22 89 (2) PCI f (MHz) I/O Pins Blocks 0 48 >67 Altera Corporation January 2011 PCI f MAX (MHz) >67 >67 >67 >67 >67 >67 MAX ...
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... Installation and The PCI Compiler is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website, Licensing www.altera.com. f For system requirements and installation instructions, refer to Software Installation and Figure 3 User Guide PCI Compiler, where <path> is the installation directory. The default installation directory on Windows is c:\altera\< ...
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... Installation and Licensing Figure 3. Directory Structure <path> Installation directory. ip Contains the Altera MegaCore IP Library and third-party IP cores. altera Contains the Altera MegaCore IP Library. common Contains shared components. ip_toolbench Contains common IP Toolbench files. pci_compiler Contains the PCI Compiler files. const_files Contains constraint files that include all necessary assignments to meet your PCI timing requirements for all supported Altera device families and development kits ...
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... After you purchase a license for PCI Compiler User Guide MegaCore function, you can request a license file from the Altera website at www.altera.com/licensing request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. f For more information on OpenCore Plus hardware evaluation, refer to ...
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... Installation and Licensing 20 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... The Altera PCI Compiler provides a complete solution for implementing a conventional PCI interface using Altera devices. It contains the Altera pci_mt64, pci_mt32, pci_t64, and pci_t32 MegaCore functions, a Verilog HDL and VHDL testbench, and reference designs. This section includes the following chapters: ■ ■ ...
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... PCI Compiler With MegaWizard Plug-In Manager Flow Section I–2 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... For more information on IP functional simulation models, refer to the Simulating Altera in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook. Use an Altera-provided PCI constraint file to meet the timing requirements of the PCI specification. f For more information on obtaining and using Altera-provided PCI constraint files in your design, refer to ...
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... PCI MegaCore This walkthrough explains how to create a custom variation of a PCI MegaCore function using the Altera PCI IP Toolbench and the Quartus II Function Design software. When you finish generating a custom variation of the PCI MegaCore function, you can incorporate it into your overall project. ...
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... Altera Corporation January 2011 Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. You can also use the Quartus II Web Edition software. Choose New Project Wizard (File menu). Click Next in the New Project Wizard: Introduction (the introduction does not display if you turned it off previously). ...
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... Under Installed Plug-Ins, expand the Interfaces>PCI folder, and click on PCI to select the PCI Compiler v10.1. Select the output file type for your design; the wizard supports VHDL and Verilog HDL. For this walkthrough, choose Verilog HDL. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... New Project Wizard. Append a variation name for the MegaCore function output files using the format <project path>\<variation name>. For this walkthrough, specify c:\altera\projects for the directory name, and pci_project.v for the output file variation name. Click Next to launch IP Toolbench for the PCI Compiler. ...
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... Click OK. Click Next to open the Advanced PCI MegaCore Features page. For this walkthrough, use the default settings for all options on this page. Click Finish to complete the parameterization of your pci_mt64 MegaCore function variation. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... For more information on PCI constraint files, refer to PCI Constraint File Tcl Altera Corporation January 2011 Only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design. ...
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... Pin Planner. A Verilog HDL or VHDL IP functional simulation model. A tcl script for assigning timing constraints to the MegaCore function. A tcl script for assigning NativeLink simulation testbench settings to the Quartus project. A MegaCore function report file. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... You can now integrate your PCI MegaCore function variation into your design and compile. Simulate the To simulate your design, you use the IP functional simulation models generated by IP Toolbench in conjunction with the Altera-provided Design PCI testbench. The IP functional simulation model is the .vo or .vho file generated as specified in files are generated in the directory you specified in the MegaWizard Plug- In Manager ...
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... For this walkthrough, follow these steps For more information on simulation using NativeLink, refer to Simulating Altera IP in Third-Party Simulation Tools the Quartus II Handbook. 1–10 PCI Compiler User Guide The IP toolbench-generated PCI testbench in the c:\altera\projects\pci_project_nativelink\verilog\pci_mt64 directory The IP functional simulation model generated as specified in 2: Set Up Simulation” on page 1–7 ...
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... Simulation in the Quartus II Software Altera provides Vector Waveform Files (.vwf) for each of the PCI MegaCore functions to perform functional simulation in the Quartus II software. The .vwf files are provided in the subdirectories at <path>\ pci_compiler\megawizard_flow\qexamples\<PCI MegaCore function>\sim. For an explanation of the provided .vwf files, refer to Quartus II Simulation Files” ...
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... BAR0 reserving 256 Megabytes (MBytes) (memory) BAR1 reserving 64 Bytes (I/O) BAR2 reserving 16 MBytes (memory) BAR3 reserving 1 MByte (memory) BAR4 reserving 64 Kilobytes (KBytes) (memory) BAR5 reserving 4 KBytes (memory) Expansion ROM BAR reserving 1 MByte (memory) PCI Compiler Version 10.1 1–11. Altera Corporation January 2011 ...
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... Target Retry Response, 64-Bit PCI, 64-Bit Local mmbw64_tret Latency Timer Expires, 64-Bit PCI, 64-Bit Local mmbw64_lte I/O Write miow Configuration Write mcfgw Altera Corporation January 2011 describes the Quartus II simulation files included in the Description Master Read Master Write PCI Compiler Version 10.1 Getting Started 1– ...
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... Target Disconnect without Data Response mmbw_tdisc_wod Target Retry Response mmbw_tret Latency Timer Expires mmbw_lte I/O Write miow Configuration Write mcfgw 1–14 PCI Compiler User Guide describes the Quartus II simulation files included in the Description Master Read Master Write PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Memory Retry, 64-Bit PCI, 64-Bit Local tmbw64_ret I/O Write tiow Expansion ROM Memory Burst Write, 64-Bit PCI, 64-Bit Local exp_rom_tmbw64 Altera Corporation January 2011 describes the Quartus II simulation files included in the Description Target Read Target Write PCI Compiler Version 10.1 Getting Started 1– ...
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... Compile the You can use the Quartus II software to compile your design. Design Altera provides constraint files to ensure that the PCI MegaCore function achieves PCI specification timing requirements in Altera devices. This walkthrough incorporates a constraint file included with PCI Compiler. f For more information on using Altera-provided constraint files in your design, refer to For instructions on compiling your design, refer to Quartus II Help ...
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... To verify the PCI timing assignments in your project, perform the following steps Altera Corporation January 2011 Open <path>\pci_example\pci_top.qpf (the pci_top project) in the Quartus II software. 1 This is the same project you created in Function Design Walkthrough” on page Choose Utility Windows > Tcl Console (View menu). ...
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... PCI MegaCore functions, refer to and For more information on setting up licensing for PCI Compiler, refer to “PCI Timing Support” on page PCI Timing Designs that use an Altera PCI Compiler MegaCore function must use an Altera-provided PCI constraint file. A PCI constraint file does the Support following: ■ ...
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... Table 1–6 Function Reference Design. The directory names are relative to the following path: where <path> is the directory in which you installed the PCI Compiler. Altera Corporation January 2011 In the Quartus II software, choose Tcl Console (View > Utility Windows menu). To source the constraint file, type the following in the Quartus II Tcl console: source pci_constraints_for_< ...
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... MegaCore Function Reference Design in the Create a new project in the Quartus II software, specifying <path>/pci_compiler/megawizard_flow/ ref_designs/pci_mt32/vhdl/chip_top.vhd as the top-level design file. Add the following directories as user libraries in the Quartus II software: <path>/pci_compiler/lib <path>/pci_compiler/megawizard_flow/ ref_designs/pci_mt32/vhdl/chip_top <path>/pci_compiler/megawizard_flow /ref_designs/pci_mt32/vhdl/pci_local PCI Compiler Version 10.1 Description Altera Corporation January 2011 ...
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... MegaCore Function Reference Design The pci_mt64 MegaCore Function Reference Design is an example that shows how to connect the local-side signals of the Altera pci_mt64 MegaCore function to local-side applications when the MegaCore function is used as a master or target on the PCI bus. The reference design consists of the following elements: ■ ...
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... This directory contains files for the SDR SDRAM controller. Create a new project in the Quartus II software, specifying the top- level design file as follows: <path>/pci_compilerv/megawizard_flow /ref_designs/pci_mt64/vhdl/chip_top.vhd Add the following directories as user libraries in the Quartus II software: <path>/pci_compiler/lib <path>/pci_compiler/megawizard_flow /ref_designs/pci_mt64/vhdl/chip_top PCI Compiler Version 10.1 Description Altera Corporation January 2011 ...
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... Select the appropriate Altera device for your project. Use an Altera-provided PCI constraint file for the device you have selected. f For more information on using PCI constraint files, refer to Appendix A, Using PCI Constraint File Tcl Compile your project. ...
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... Using the Reference Designs 1–24 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Settings When turned on, the PCI 66-MHz Capable option sets bit 5 of the PCI configuration space status register. For more information on the function of this register, refer to Altera Corporation January 2011 2. Parameter Settings “PCI MegaCore Function Settings” “Read-Only PCI Configuration Registers” ...
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... Parameterize - PCI Compiler wizard. 2–2 PCI Compiler User Guide Device ID Vendor ID Revision ID Subsystem ID Subsystem Vendor ID Minimum Grant Maximum Latency Class Code 3–28. Use hardwired BARs in closed systems only. PCI Compiler Version 10.1 “Configuration Registers” Altera Corporation January 2011 ...
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... When CompactPCI technology is selected on the initial page of the wizard, the capabilities list pointer register on the Advanced PCI MegaCore Function Features page is automatically turned on with the default value of 0x40. Altera Corporation January 2011 3–37. PCI Compiler Version 10.1 Parameter Settings “ ...
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... PCI Compiler User Guide 3–28. Allow Variable Byte Enables During Burst Transactions Use in Host Bridge Application Allow Internal Arbitration Logic Disable Master Latency Timer Assume ack64n Response PCI Compiler Version 10.1 “Configuration Registers” on Altera Corporation January 2011 ...
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... I/Os. Turning on Allow Internal Arbitration Logic removes the tri-state buffer from the reqn signal output, allowing the signal to be connected to internal FPGA logic and eliminating the need to use additional device I/O resources or board traces. Altera Corporation January 2011 3–127. PCI Compiler Version 10.1 Parameter Settings “ ...
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... Disabling the master latency timer can also result in increased latency for other master devices in the system. If increased latency for other master devices is unacceptable in your application, this option should not be used. 3–121. PCI Compiler Version 10.1 “64-Bit Single Cycle Memory Altera Corporation January 2011 ...
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... Variation File If you do not want to use the IP Toolbench Parameterize - PCI Compiler wizard, you can specify Altera PCI MegaCore function parameters Parameters directly in the hardware description language (HDL) or graphic design files. Table 2–1. PCI MegaCore Function Parameters (Part Name Format Hexadecimal DEVICE_ID ...
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... Device vendor ID register. This parameter is a 16-bit hexadecimal value that sets the vendor ID register in the PCI configuration space. The value for this parameter can be the Altera vendor ID (1172 Hex) or any other PCI SIG-assigned vendor ID number. H"FFF00000" Base address register (BAR) zero. When ...
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... Table 2–1. PCI MegaCore Function Parameters (Part Name Format Hexadecimal HARDWIRE_BARn Hexadecimal HARDWIRE_EXP_ROM Altera Corporation January 2011 Default Value H"FF000000" Hardwire base address register. n corresponds to the base address register number and can be from HARDWIRE_BARn is a 32-bit hexadecimal value that permanently sets the value stored in the corresponding BAR ...
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... H"00000000" during a configuration read to CIS when CIS_PTR_ENA is set to 0. H"00000000" Feature enable bits. This parameter is a 32-bit hexadecimal value which controls whether various features are enabled or disabled. The bit definition of this parameter is shown in PCI Compiler Version 10.1 Description Table 2–2. Altera Corporation January 2011 ...
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... Bit Name Number 5..0 HARDWIRE_BARn_ENA 6 HARDWIRE_EXP_ROM_ENA 7 EXP_ROM_ENA Altera Corporation January 2011 Default Value H"01" Interrupt pin register. This parameter indicates the value of the interrupt pin register in the configuration space address location 3DH. This parameter can be set to two possible values: H"00" to indicate that no interrupt support is needed, or H" ...
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... If this bit is set to 1, the tri-state buffer on the reqn signal is removed, allowing an arbiter to be implemented without using device pins for the reqn and gntn signals. PCI Compiler Version 10.1 Definition Altera Corporation January 2011 ...
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... If starting a new design, Altera recommends adding the data steering logic in the local side application for lower logic utilization and better overall performance. PCI Compiler Version 10.1 ...
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... PCI Compiler Version 10.1 Definition or pci_mt32 master to is gntn pci_mt64 master will relinquish bus ack64n one clock cycle after the assertion , configuration, and I/O Altera Corporation January 2011 ...
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... Reserved Note to Table 2–2: (1) These parameters affect master functionality and therefore only affect the pci_mt64 and pci_mt32 MegaCore functions. Altera Corporation January 2011 Default Value standard master burst transaction the byte enables accompanying the initial data word provided by the local side are used throughout the master burst transaction ...
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... Variation File Parameters 2–16 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... The functions consist of several blocks: ■ ■ ■ ■ ■ ■ ■ Altera Corporation January 2011 3. Functional Description “Functional Overview” “PCI Bus Signals” “PCI Bus Signals” “PCI Bus Commands” “Configuration Registers” “Target Mode Operation” ...
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... Byte Enable Control Local Target Control PCI Compiler Version 10.1 cmd_reg[6..0] stat_reg[6..0] cache[7..0] lm_req32n lm_req64n lm_lastn lm_rdyn lm_ackn lm_adr_ackn lm_dxfrn lm_tsr[9..0] l_adi[63..0] l_cbeni[7..0] l_dato[63..0] l_adro[63..0] l_beno[7..0] l_cmdo[3..0] l_ldat_ackn l_hdat_ackn lt_rdyn lt_discn lt_abortn lirqn lt_framen lt_ackn lt_dxfrn lt_tsr[11..0] Altera Corporation January 2011 ...
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... PCI Master framen irdyn PCI Target trdyn devseln stopn intan par Parity Checker & perrn Generator serrn Altera Corporation January 2011 pci_mt32 Parameterized Configuration Registers Local Master Control Control Local Address/ Data/Command/ Byte Enable Control Local Target Control PCI Compiler Version 10.1 Functional Description cmd_reg[6 ...
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... PCI Compiler User Guide pci_t64 Parameterized Configuration Registers Local Address/ Data/Command/ Byte Enable Control Local Target Control PCI Compiler Version 10.1 cmd_reg[6..0] stat_reg[6..0] l_adi[63..0] l_dato[63..0] l_adro[63..0] l_beno[7..0] l_cmdo[3..0] l_ldat_ackn l_hdat_ackn lt_rdyn lt_discn lt_abortn lirqn lt_framen lt_ackn lt_dxfrn lt_tsr[11..0] Altera Corporation January 2011 ...
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... Data Buffer cben[3..0] framen irdyn PCI Target trdyn devseln stopn intan par Parity Checker & perrn Generator serrn Altera Corporation January 2011 pci_t32 Parameterized Configuration Registers Local Address/ Data/Command/ Byte Enable Control Local Target Control PCI Compiler Version 10.1 Functional Description cmd_reg[6 ...
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... The PCI MegaCore function has decoded a valid address for one of its BARs and it accepts the transactions (assert devseln) The PCI MegaCore function is ready for the data transfer (assert trdyn) PCI Compiler Version 10.1 Error perrn Reporting serrn Signals Interrupt intan Request Signal Altera Corporation January 2011 ...
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... A retry occurs before the first data phase. (2) A device must assert the devseln signal for at least one clock before it signals an abort. Altera Corporation January 2011 When both trdyn and irdyn are active, a data word is clocked from the sending to the receiving device ...
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... During data phases, data is driven over the ad[63..0] bus and byte enables are driven over the cben[7..0] bus. Additionally, parity for ad[63..32] and cben[7..4] is presented over the par64n signal. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... PCI bus arbiter and after the bus idle state is detected, the function initiates the address phase by asserting framen, driving the PCI address on ad[31..0], and driving the bus command on cben[3..0] for one clock cycle. 1 Altera Corporation January 2011 illustrates the PCI-compliant master device signals that clk System ...
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... The master device should stop the current transaction The master device should abort the current transaction shows the possible control signal combinations on the PCI bus “Master Mode Operation” on page 3–134 PCI Compiler Version 10.1 for more for more information Altera Corporation January 2011 ...
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... Input gntn Input l_dis_64_extn Output reqn Altera Corporation January 2011 Input—Standard input-only signal Output—Standard output-only signal Bidirectional—Tri-state input/output signal Sustained tri-state (STS)—Signal that is driven by one agent at a time (e.g., device or host operating on the PCI bus). An agent that drives a sustained tri-state pin low must actively drive it high for one clock cycle before tri-stating it ...
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... For data phases, req64n is asserted irdyn is asserted on a read trdyn pci_mt32 input is a chip select for idsel is initially asserted, the address and and ad[63..0] and only for ad[31..0] cben[3..0] signal remains asserted during Altera Corporation January 2011 , ...
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... STS ack64n (1) STS trdyn STS (1) stopn STS perrn Open-Drain Low serrn Altera Corporation January 2011 Polarity Low Request 64-bit transfer. The the current bus master and indicates that the master is requesting a 64-bit transaction This signal is not implemented in framen pci_t32 . Low Initiator ready. The ...
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... The PCI MegaCore functions assert only when the local side asserts the intan the bit (bit 10 of the command register int_dis PCI Compiler Version 10.1 Description signal is an active-low interrupt to the signal and lirqn Altera Corporation January 2011 ...
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... Note to Table 3–4: (1) This signal is added for compliance with the PCI Local Bus Specification, Revision 3.0. Altera Corporation January 2011 summarizes the PCI local interface signals for the Polarity – Cache line-size register output. The the same as the configuration space cache line-size register. ...
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... Master abort received. Status register bit 13. Signaled system error. Status register bit 14. Parity error detected. Status register bit 15. Interrupt status. Status register bit 3. (1) summarizes the PCI local interface signals for the address, data, PCI Compiler Version 10.1 Description Altera Corporation January 2011 ...
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... Input – l_adi[63..0] Input – l_cbeni[7..0] Altera Corporation January 2011 Description Local address/data input. This bus is a local-side time multiplexed address/data bus. This bus changes operation depending on the function you are using and the type of transaction. During master transactions, the local side must provide the address ...
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... B"000" PCI Compiler Version 10.1 bus is driven active during pci_mt64 and pci_t64 l_dato[63..0] l_dato[31.. pci_mt64 l_ldat_ackn not. bus is driven by the functions implement only and pci_mt64 pci_t64 bus. During 32-bit to indicate whether the address boundary ( QWORD ad[2..0] = Altera Corporation January 2011 ...
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... Output Low l_ldat_ackn Output Low l_hdat_ackn Altera Corporation January 2011 Description Local command output. The l_cmdo[3..0] MegaCore functions during target transactions. It has the bus command and the same timing as the command is encoded as presented on the PCI bus. Local low data acknowledge. The l_ldat_ackn during target write and master read transactions ...
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... The PCI bus specification requires that a PCI target issues a disconnect whenever the transaction exceeds its memory space. When using PCI MegaCore functions, the local side is responsible for asserting its memory space. PCI Compiler Version 10.1 Description input lt_discn if the transaction crosses lt_discn Altera Corporation January 2011 ...
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... Output lt_framen Output lt_ackn Output lt_dxfrn Altera Corporation January 2011 Polarity Low Local target ready. The local side asserts a valid data input during target read, or ready to accept data input during a target write. During a target read, deassertion suspends the current transfer (i.e., a wait state is inserted by the local side) ...
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... PCI bus interrupt. Asserting this lirqn signal forces the PCI MegaCore function to assert the signal for as long as the int_dis bit (bit 10 of the command register PCI Compiler Version 10.1 Description lt_tsr 11..0] [ Table 3–8. intan signal is asserted and the lirqn Altera Corporation January 2011 ...
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... Altera Corporation January 2011 shows definitions for the local target transaction status register Description Base address register hit. Asserting that the PCI address matches that of a base address register and that the PCI MegaCore function has claimed the transaction. Each ...
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... When lm_req64n requests a 64-bit pci_mt64 ack64n signal, ack64n boundary. This signal is not implemented signal should be asserted only after master interface ends the as soon as framen to indicate that the last data phase has Altera Corporation January 2011 ...
Page 99
... Output lm_ackn Output lm_dxfrn Output lm_tsr[9..0] Altera Corporation January 2011 Low Local master ready. The local side asserts the indicate a valid data input during a master write, or ready to accept data during a master read. During a master write, the signal de-assertion suspends the current transfer (i.e., wait state is inserted by the local side) ...
Page 100
... Because ack64n pci_mt32 PCI Compiler Version 10.1 or function is pci_mt32 signal). The reqn signal is gntn or pci_mt32 function has or function pci_mt32 or pci_mt64 pci_mt32 or pci_mt64 pci_mt32 or pci_mt64 or pci_mt64 does not request 64-bit Altera Corporation January 2011 ...
Page 101
... I/O read/write, and configuration read/write commands. The bus commands are discussed in greater detail in “Target Mode Operation” on page 3–44 on page Altera Corporation January 2011 shows the PCI bus commands that can be initiated or Bus Command Cycle Interrupt acknowledge 0000 ...
Page 102
... SIG) PCI Local Bus Specification, Revision 3.0 and the Compliance Checklist, Revision 3.0. These specifications define two header formats, type one and type zero. Header type one is used for PCI-to-PCI bridges; header type zero is used for all other devices, including the Altera PCI MegaCore functions. 3–28 PCI Compiler User Guide PCI Compiler Version 10 ...
Page 103
... PCI bus agents. You can set some of the read-only registers when creating a custom PCI design by using the IP Toolbench Parameterize - PCI Compiler wizard. For example, you can change the Altera Corporation January 2011 shows the defined 64-byte configuration space. The registers ...
Page 104
... Base address register one Base address register two Base address register three Base address register four Base address register five CardBus CIS pointer Subsystem vendor ID Subsystem ID Expansion ROM BAR Capabilities pointer Interrupt line Interrupt pin Minimum grant (1) (1) Maximum latency Altera Corporation January 2011 ...
Page 105
... Vendor 16-bit read-only register that identifies the manufacturer of the device. The value of this register is assigned by the PCI SIG; the default value of this register is the Altera vendor ID value, which is 0x1172. However, by setting the ven_id value through the wizard, you can change the value of the vendor ID register to your PCI SIG-assigned vendor ID value. Refer to Table 3– ...
Page 106
... PCI Compiler Version 10.1 lets the function respond to io_ena mem_ena lets the function allows the function to request when PCI master 1 enables the function to perr_ena output. allows the function to serr_ena output. However, to signal serrn bit must also be high. Altera Corporation January 2011 ...
Page 107
... Unused 8 dat_par_rep 10..9 devsel_tim Altera Corporation January 2011 Table 3–17. Read/Write – Reserved. Read Interrupt status. This bit is read only and is set when the bit (bit 10 of the command register and int_dis is asserted on the PCI bus. This signal is driven to ...
Page 108
... The value of this register is assigned by the manufacturer (e.g., Altera for the PCI MegaCore functions.) For the Altera PCI MegaCore functions, the default value of the revision ID register is the revision number of the function. Refer to can change the value of the revision ID register through the wizard. ...
Page 109
... The local side must use this value when using the memory read line, memory read multiple, and memory write and invalidate commands in master mode. Refer to 1 Table 3–20. Cache Line Size Register Format Altera Corporation January 2011 Table 3–19. Data Bit Mnemonic 23 ...
Page 110
... Data Bit Mnemonic 2..0 lat_tmr 7..3 lat_tmr Table 3–22. Data Bit Mnemonic 7..0 header PCI Compiler Version 10.1 3–21. Read/Write Definition Read Latency timer register Read/write Latency timer register Read/Write Definition Read PCI header type Altera Corporation January 2011 ...
Page 111
... Bit memory BAR controls whether the BAR is prefetchable. If you choose the prefetchable memory option for an individual BAR in the wizard, bit 3 of the corresponding BARn parameter will be updated. Altera Corporation January 2011 Type of address space reserved by the BAR Location of the reserved memory ...
Page 112
... Memory prefetchable. The pre_fetch of memory are prefetchable by the host bridge. Base address registers. PCI Compiler Version 10.1 bit indicates whether the blocks Altera Corporation January 2011 ...
Page 113
... BARn basis and sets the corresponding parameters accordingly. When using the hardwire BAR feature, the corresponding BARn attributes must indicate the appropriate BAR settings, such as size and type of address space. 1 Altera Corporation January 2011 Reserved memory space can be calculated by the following (40 – 8) formula GBytes, where 40 = actual available registers and 8 = user assigned read/write register ...
Page 114
... CIS pointer register is pointing to an expansion ROM space. Data Bit Mnemonic Read/Write 15..0 sub_ven_id PCI Compiler Version 10.1 shows this register’s format. For Definition Table 3–26. The default Definition Read PCI subsystem/vendor ID Altera Corporation January 2011 ...
Page 115
... Read/Write Bit 0 Read/write adr_ena 10..1 Reserved – 31..11 Read/write bar Altera Corporation January 2011 3–27. The default value of the subsystem ID register is 0x0000. Data Bit Mnemonic Read/Write 15..0 sub_id 3–28. Address decode enable. The adr_ena device accepts accesses to its expansion ROM. You can disable the expansion ROM address space by setting this bit to 0 ...
Page 116
... When implementing a hardwire expansion ROM BAR, the corresponding BARs become read only. However, bit 0 is read/write, allowing you to disable the expansion ROM BAR after power-up. 3–29. Data Bit Mnemonic Read/Write Read/write cap_ptr PCI Compiler Version 10.1 Definition Capabilities pointer register Altera Corporation January 2011 ...
Page 117
... PCI bus. The value set in this register indicates the required burst period length in 250-ns increments. You can set this register through the wizard. Refer to Table Table 3–32. Minimum Grant Register Format Altera Corporation January 2011 Data Bit Mnemonic Read/Write 7 ...
Page 118
... Data Bit Mnemonic 7..0 max_lat Table 3–34 lists the PCI and local side signals that apply for pci_t64 PCI Signals ad[31..0] v cben[3.. PCI Compiler Version 10.1 Read/Write Definition Read Maximum latency register pci_mt32 pci_t32 ad[31..0] cben[3.. Altera Corporation January 2011 ...
Page 119
... Altera Corporation January 2011 pci_t64 Local-Side Datapath Signals v l_adi[31..0] l_cbeni[3..0] v l_adro[31..0] v l_dato[31..0] v l_beno[3.. Target Local-Side Control Signals Master Local-Side Control Signals PCI Compiler Version 10 ...
Page 120
... I/O transactions. For memory read transactions, these functions automatically read 64-bit data on the local side and transfer the data to the PCI master, one DWORD at a time, if the PCI bus is 32 bits wide. PCI Compiler Version 10.1 pci_mt32 pci_t32 Altera Corporation January 2011 ...
Page 121
... PCI MegaCore function to terminate the transactions with a retry or target abort. Because all I/O transactions are single-cycle, terminating a transaction with a disconnect does not apply. Altera Corporation January 2011 “Target Transaction Terminations” on page 3–77 The PCI MegaCore function treats the memory read line and memory read multiple commands as memory read ...
Page 122
... If the address of the transaction matches the memory range specified in a base address register, the PCI MegaCore function turns on the drivers for the ad bus, devseln, trdyn, stopn, and par (as well as par64 and ack64n for 64-bit transactions) in the following clock cycle. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
Page 123
... Altera Corporation January 2011 The PCI MegaCore function drives and asserts devseln (and ack64n for 64-bit transactions) to indicate to the master device that it is accepting the transaction. One or more data phases follow, depending on the type of read transaction. PCI Compiler Version 10.1 Functional Description 3– ...
Page 124
... This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions. 3–50 PCI Compiler User Guide shows the waveform for a 64-bit single-cycle memory read Adr BE0_L BE0_H Adr-PAR Z Adr D0_L D0_H 000 181 PCI Compiler Version 10 D0_L D0_H D0-L-PAR D0-H-PAR 6 BE0_L BE0_H 581 000 Altera Corporation January 2011 ...
Page 125
... The rising edge of clock cycle 7 registers the valid data from the data on the bus. At the same time, the PCI MegaCore function asserts the ad to indicate that there is valid data on the Altera Corporation January 2011 shows the sequence of events for a 64-bit single-cycle memory Event signals and asserts ...
Page 126
... PCI Compiler Version 10.1 , and ack64n to end the high during this clock cycle. bus because the cycle is complete. ad framen lt_framen , and Altera Corporation January 2011 is ...
Page 127
... In other words, if lt_tsr[9] is asserted during a valid target transaction, it indicates that the impending transaction is a burst, but if lt_tsr[9] is not asserted it may or may not indicate that the transaction is single-cycle. Altera Corporation January 2011 Figure 3–8 illustrates a burst memory read target Figure 3– 64-bit zero-wait state burst Figure 3– ...
Page 128
... D0-H-PAR D0_L D1_L D0_H D1_H 381 PCI Compiler Version 10 D1_L D2_L D3_L D1_H D2_H D3_H BE1_L BE2_L BE3_L BE2_H BE1_H BE3_H D0-L-PAR D1-L-PAR D2-L-PAR D3-L-PAR D1-H-PAR D2-H-PAR D3-H-PAR Adr 6 D2_L D3_L D4_L D2_H D3_H D4_H 781 000 Altera Corporation January 2011 13 ...
Page 129
... Note to Figure 3–9: (1) This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions. Altera Corporation January 2011 shows the same transaction D0_L Z D0_H BE0_L BE0_H Z D0-L-PAR D0-H-PAR Adr ...
Page 130
... BE0_H Z D0-H-PAR D0_L D0_H 381 PCI Compiler Version 10.1 Figure 3–8 with the D1_L D2_L D1_H D2_H Z BE2_L BE1_L BE1_H BE2_H D0-L-PAR D1-L-PAR D2-L-PAR D1-H-PAR D2-H-PAR Adr 6 D1_L D2_L D3_L D1_H D2_H D3_H 781 381 781 Altera Corporation January 2011 13 000 ...
Page 131
... The sequence of events in except for the following cases: ■ ■ ■ Altera Corporation January 2011 shows a 32-bit single-cycle mismatched bus width memory Figure 3–7 for the description of a 32-bit single-cycle Figure 3–11 ...
Page 132
... The pci_mt64 and the pci_t64 functions always transfer 64-bit data on the local side 32-bit single-cycle memory read transaction, only one DWORD is transferred to the PCI master BE0_L Adr-PAR Z D0_L D0_H 101 PCI Compiler Version 10 D0_L D0-L-PAR Adr 6 BE0_L BE0_L BE0_H BE0_H 501 000 Altera Corporation January 2011 ...
Page 133
... DWORD is transferred to the PCI side, as shown in Figure 3–12 Altera Corporation January 2011 shows a 32-bit PCI side and 64-bit local side burst memory Figure 3–12 are the same as those shown in Figure 3– ...
Page 134
... The value on ad[31..0] is not a QWORD address boundary (ad[2..0] == B”100”). 3–60 PCI Compiler User Guide BE0_H BE0_H Z D0_L D1_L D0_H D1_H BE0_H 301 PCI Compiler Version 10 D0_H D1_H D1_H D1_L BE2_H BE2_H BE1_L D1-L-PAR D1-H-PAR D0-H-PAR Adr 6 D2_L D2_H BE1_L BE1_H 701 000 Altera Corporation January 2011 13 ...
Page 135
... Altera Corporation January 2011 3–13, lt_tsr[11..0] indicates that the base address register The PCI MegaCore functions do not ensure that the combination of the ad[1..0] and cben[3..0] signals is valid during the address phase of an I/O transaction. Local side logic should implement this functionality if performing I/O transactions ...
Page 136
... PCI MegaCore functions assert trdyn independent from the lt_rdyn signal The local side cannot retry, disconnect, or abort configuration cycles BE0_L Adr-PAR Z 100 PCI Compiler Version 10.1 Figure 3–14. The configuration read D0_L D0-L-PAR 500 000 Altera Corporation January 2011 ...
Page 137
... For all memory write transactions, the following sequence of events is the same Altera Corporation January 2011 Memory write I/O write Configuration write Single-cycle memory write Burst memory write Mismatched bus width memory write Mismatched bus-width transactions are 32-bit PCI transactions performed by the pci_mt64 and pci_t64 MegaCore functions ...
Page 138
... This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions. 3–64 PCI Compiler User Guide shows the waveform for a 64-bit single-cycle memory write D0_L D0_H 7 BE0_L BE0_H Adr-PAR D0-L-PAR D0-H-PAR Adr 7 BE0_L BE0_H 181 PCI Compiler Version 10 D0_L D0_H 581 000 Altera Corporation January 2011 ...
Page 139
... The PCI MegaCore function asserts 6 Because is already asserted, this clock cycle is the first and last data phase in this cycle. irdyn Altera Corporation January 2011 shows the sequence of events for a 64-bit single-cycle memory Event to indicate that only one data phase remains in the ...
Page 140
... PCI side has lt_tsr[11..0] lt_framen indicating to the local side that no additional PCI Compiler Version 10.1 bus and drives the data on the ad signal to indicate lt_ackn l_beno bus. Because , devseln , and ack64n to end the Altera Corporation January 2011 ...
Page 141
... In other words, if lt_tsr[9] is asserted during a valid target transaction, it indicates that the impending transaction is a burst, but if lt_tsr[9] is not asserted it may or may not indicate that the transaction is single-cycle. Altera Corporation January 2011 shows a 64-bit zero-wait state burst memory write target PCI Compiler Version 10.1 Functional Description Figure 3– ...
Page 142
... D1_H BE1_L BE0_L BE1_H BE0_H 381 PCI Compiler Version 10 D3_L D4_L D3_H D4_H BE3_L BE4_L BE3_H BE4_H D2-L-PAR D3-L-PAR D4-L-PAR D2-H-PAR D3-H-PAR D4-H-PAR D2_L D3_L D4_L D2_H D3_H D4_H BE2_L BE3_L BE4_L BE2_H BE3_H BE4_H 781 000 Altera Corporation January 2011 14 ...
Page 143
... Note to Figure 3–17: (1) This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions. Altera Corporation January 2011 shows the same transaction D0_L D1_L D0_H D1_H BE0_L BE1_L BE0_H BE1_H ...
Page 144
... D1_L D0_H D1_H BE1_L BE0_L BE1_H BE0_H 381 781 PCI Compiler Version 10.1 Figure 3–16 with the local D3_L D3_H BE3_L BE3_H D2-L-PAR D3-L-PAR D2-H-PAR D3-H-PAR D2_L D3_L D2_H D3_H BE2_L BE3_L BE2_H BE3_H 381 781 000 Altera Corporation January 2011 14 ...
Page 145
... The sequence of events in except for the following: ■ ■ ■ Altera Corporation January 2011 shows a 32-bit single-cycle mismatched bus width memory Figure 3–15 for a description of a 32-bit single cycle memory Figure 3–19 is exactly the same as in ...
Page 146
... Note to Figure 3–19: (1) Ignore this signal for this transaction. 3–72 PCI Compiler User Guide 3–19, the local-side transfer occurs in clock cycle 7 because D0_L BE0_L Adr-PAR D0-L-PAR Adr Adr 7 101 PCI Compiler Version 10 D0_L BE0_L 000 501 Altera Corporation January 2011 11 ...
Page 147
... Figure 3–20 the pci_mt32 and pci_t32 functions, waveforms for a 32-bit burst memory write transaction, excluding the 64-bit extension signals as noted. Altera Corporation January 2011 shows a 32-bit burst memory write transaction; the events are Figure 3–17. The main difference between the two figures is Figure 3– ...
Page 148
... PCI Compiler User Guide D2_L D0_L D1_L BE2_L BE0_L BE1_L D0-L-PAR D1-L-PAR Adr 7 D0_L D1_L BE0_L BE1_L 301 PCI Compiler Version 10 D3_L D4_L BE3_L BE4_L D2-L-PAR D3-L-PAR D4-L-PAR D2_L D3_L D4_L BE2_L BE3_L BE4_L 701 000 Altera Corporation January 2011 14 ...
Page 149
... Altera Corporation January 2011 The PCI MegaCore functions do not ensure that the combination of the ad[1..0] and cben[3..0] signals is valid during the address phase of an I/O transaction. Local side logic should implement this functionality if performing I/O transactions. ...
Page 150
... Because the configuration write does not require local side actions, the PCI MegaCore function asserts trdyn independent from the lt_rdyn signal The local side cannot retry, disconnect, or abort configuration cycles D0_L BE0_L Adr-PAR D0-L-PAR 100 PCI Compiler Version 10 500 000 Altera Corporation January 2011 11 ...
Page 151
... In a read transaction, the local-side device can request a retry as long as data has not been transferred to the PCI MegaCore function. MegaCore functions, excluding the 64-bit signals as noted for pci_mt32 and pci_t32. Altera Corporation January 2011 PCI Compiler Version 10.1 Functional Description Figure 3–23 applies to all PCI 3– ...
Page 152
... This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. 3–78 PCI Compiler User Guide Adr D0_L D0_H 7 BE0_L BE0_H Adr-PAR D0-L-PAR D0-H-PAR PCI Compiler Version 10 D1-L D1_H BE1_L BE1_H D1-L-PAR D1-H_PAR Adr 7 BE0_L BE0_H 381 000 Altera Corporation January 2011 ...
Page 153
... PCI bus. You can use lt_ackn and lt_dxfrn to check the number of DWORDs transferred on the local side and use lt_tsr[10] to check the number of DWORDs transferred on the PCI bus. 1 Altera Corporation January 2011 The PCI Local Bus Specification, Revision 3.0 requires that a target device issues a disconnect if a burst transaction goes beyond its address range ...
Page 154
... PCI MegaCore functions, excluding the 64-bit Adr D0_L D0_H 7 BE0_L BE0_H Adr-PAR D0-L-PAR D0-H-PAR Adr 7 BE0_L BE0_H 000 381 PCI Compiler Version 10.1 Figure 3– D1-L D1_H BE1_L BE1_H D1-L-PAR D1-H_PAR D0_L D0_H 781 381 000 Altera Corporation January 2011 ...
Page 155
... Note to Figure 3–25: (1) This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. Altera Corporation January 2011 shows an example of a disconnect during a burst target write D0_L D1_L D2_L D0_H D1_H D2_H BE0_L ...
Page 156
... This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. 3–82 PCI Compiler User Guide shows an example of a disconnect during a burst read 3–26, lt_rdyn is asserted in clock cycle 5 and lt_discn BE0_L BE0_H Adr-PAR Z D0_L D0_H 381 PCI Compiler Version 10 D0_L D0_H D0-L-PAR D0-H-PAR Adr 6 781 381 000 Altera Corporation January 2011 11 ...
Page 157
... Note to Figure 3–27: (1) This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. Altera Corporation January 2011 shows an example of a disconnect during a burst target read D0_L D1_L Z D0_H D1_H BE0_L ...
Page 158
... PCI Compiler User Guide shows an example of a disconnect during a 32-bit read BE0_L BE0_H Adr-PAR Z D0_L D0_H 101 PCI Compiler Version 10 D0_L D0_H D0-L-PAR D0-H-PAR Adr 6 BE0_L BE0_H 501 000 Altera Corporation January 2011 ...
Page 159
... Altera Corporation January 2011 shows an example of a disconnect during a 32-bit read BE0_L BE0_H Z Adr-PAR Adr D0_L D0_H 101 PCI Compiler Version 10.1 ...
Page 160
... This condition most commonly occurs during I/O transactions. The local-side device must ensure that this requirement is met, and if it receives this type of transaction, it must assert lt_abortn to request a target abort termination. PCI Compiler Version 10.1 “Status Register” shows the PCI MegaCore Altera Corporation January 2011 ...
Page 161
... Note to Figure 3–30: (1) This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. Altera Corporation January 2011 D0_L D1-L D0_H D1_H BE0_L BE1_L BE1_H BE0_H D0-L-PAR D1-L-PAR ...
Page 162
... Master Mode Operation Additional Design Guidelines for Target Transactions Altera recommends that the local-side application deassert the lt_rdyn signal after the target transaction completes to avoid false triggering of internal state machines if the next target transaction begins immediately. You can detect that the current target transaction has completed if lt_ackn and lt_tsr[8] are both deasserted ...
Page 163
... Altera Corporation January 2011 Table 3–37 lists the PCI and local side signals that apply for each Signal Name pci_mt64 PCI Signals ...
Page 164
... Assume ack64n Response option is turned on in the Parameterize - PCI Compiler wizard. For more information on the Assume ack64n Response option, refer to “Assume ack64n Response” on page PCI Compiler Version 10.1 pci_mt32 2–6. Altera Corporation January 2011 ...
Page 165
... Therefore, the local side must implement any special handling required by these commands. The function outputs the cache line size register value to the local side for this purpose. Altera Corporation January 2011 32-bit burst memory read/write 32-bit single-cycle memory read/write ...
Page 166
... The local-side design must ensure that PCI latency rules are not violated while the function waits for data. Therefore, the local-side device must not insert more than eight wait states before asserting lm_rdyn. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
Page 167
... For each type of transaction, the following sequence of events is the same Altera Corporation January 2011 Memory read I/O and configuration read Burst memory read Single-cycle memory read Mismatched bus width memory read Mismatched bus-width transactions are 32-bit PCI transactions performed by the pci_mt64 MegaCore function. ...
Page 168
... This process is necessary because the pci_mt64 function must release the bus so another PCI agent can drive it. A PCI target asserts devseln to claim the transaction. One or more data phases follow, depending on the type of read transaction. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
Page 169
... Notes to Figure 3–31: (1) This signal is not applicable to the pci_mt32 MegaCore function. (2) For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions. Altera Corporation January 2011 shows the waveform for a 64-bit zero-wait state burst Adr Z D0_L ...
Page 170
... PCI MegaCore function does not assert gntn in less than three clock cycles, refer to PCI Compiler Version 10.1 Figure 3–31 shows is asserted, this action gntn to be gntn and are framen irdyn . l_cbeni “Design Consideration” on page 3–92 Altera Corporation January 2011 ...
Page 171
... The last data phase on the PCI side takes place during clock cycle 10. The function also asserts successful data transfer has occurred on the PCI bus during the previous clock cycle. Altera Corporation January 2011 Event to inform the target that the function is ready to receive data. On the first ...
Page 172
... PCI Compiler Version 10.1 framen , informing the local side that the function lm_ackn . The assertion of the lm_dxfrn are deasserted, indicating that the current , informing the local side that the function lm_ackn . The assertion of the lm_dxfrn l_dato Altera Corporation January 2011 bus ...
Page 173
... Note to Figure 3–32: (1) This signal is not applicable to the pci_mt32 MegaCore function. Altera Corporation January 2011 shows the same transaction Adr Z D0_L 0 6 BE_L Adr-PAR Z Adr BE_L ...
Page 174
... PCI Compiler Version 10.1 Figure 3–31 with the local D1_L D2_L Z D1_H D2_H Z Z BE_L Z BE_H D0-L-PAR D1-L-PAR D2-L-PAR D0-H-PAR D1-H-PAR D2-H-PAR D0_L D1_L D2_L D0_H D1_H D2_H 308 208 308 200 000 Altera Corporation January 2011 ...
Page 175
... Data transfer is suspended on the PCI side in clock cycle 9 and on the local side in clock cycle 10. Altera Corporation January 2011 shows the same transaction as in PCI Compiler Version 10.1 Functional Description Figure 3– ...
Page 176
... D1_L 0 Z D0_H D1_H 0 6 BE_L 0 BE_H Adr-PAR Z D0-L-PAR Z D0-H-PAR Adr 6 BE_L BE_H D0_L D0_H 002 004 008 208 308 PCI Compiler Version 10 D2_L Z D2_H D1-L-PAR D2-L-PAR D1-H-PAR D2-H-PAR D1_L D2_L D1_H D2_H 208 308 200 000 Altera Corporation January 2011 ...
Page 177
... If your application is a system that has only 64-bit PCI devices and the local side wants to transfer one 64-bit data word, Altera recommends that you perform a 64-bit single-cycle memory read master transaction. However, if your application is a ...
Page 178
... For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions. 3–104 PCI Compiler User Guide Adr Z D0_L 0 Z D0_H 0 6 BE_L 0 BE_H Z Adr-PAR Z Adr BE_L 6 BE_H 002 004 008 208 PCI Compiler Version 10 D0-L-PAR D0-H-PAR D0_L D0_H 308 200 000 Altera Corporation January 2011 ...
Page 179
... Note to Figure 3–36: (1) This signal is not applicable to the pci_mt32 MegaCore function. Altera Corporation January 2011 shows a 32-bit single cycle memory read master transaction. Figure 3–36 3–35, except that in Figure 3– Adr 0 ...
Page 180
... In this transaction, the local-side master interface Because the local-side master interface is 64 bits and the PCI target is only 32 bits, these transactions always begin on 64-bit boundaries, which results in l_ldat_ackn always asserted first. PCI Compiler Version 10.1 Figure 3–37 are the same as those Altera Corporation January 2011 ...
Page 181
... I/O & Configuration Read Transactions I/O and configuration read transactions by definition are 32 bits wide. The sequence of events is the same 32-bit single-cycle memory read master transaction, as shown in the pci_mt64 and pci_mt32 MegaCore functions, excluding the 64-bit extension signals as noted for pci_mt32. Altera Corporation January 2011 ...
Page 182
... At the same time, the pci_mt64 or pci_mt32 function turns on the drivers for framen (and req64n, in the case of a 64-bit transaction.) PCI Compiler Version 10.1 Altera Corporation January 2011 ...
Page 183
... Any additional requirements for the memory write and invalidate command must be implemented by the local-side design. Altera Corporation January 2011 The PCI function begins the PCI address phase. During the PCI address phase, the local side must provide the byte enables for the transaction on the l_cbeni bus ...
Page 184
... D0-L-PAR D0-H-PAR Adr D0_L D1_L D0_H D1_H 7 BE_L BE_H 002 004 008 208 PCI Compiler Version 10 D2_L D3_L Z D1_L D1_H D2_H D3_H Z Z BE_L Z BE_H D1-L-PAR D2-L-PAR D3-L-PAR D2-H-PAR D3-H-PAR D1-H-PAR D2_L D3_L D3_H D2_H 308 000 Altera Corporation January 2011 ...
Page 185
... For subsequent data phases, the PCI MegaCore function asserts The PCI MegaCore function continues to assert its The function also asserts Altera Corporation January 2011 shows the sequence of events for a 64-bit zero-wait state burst Event to request a 64-bit transaction ...
Page 186
... PCI Compiler Version 10.1 l_cbeni “Allow for more information about this lm_ackn is asserted in the current and lm_dxfrn “Design Consideration” on page 3–92 to inform the local side that data during the irdyn . is lm_ackn . The assertion of the lm_dxfrn Altera Corporation January 2011 , ...
Page 187
... PCI bus during the previous clock cycle. The function deasserts 13 completed. Altera Corporation January 2011 Event are asserted, the second 64-bit data word is transferred to the PCI side to inform the local side that the PCI side is ready to accept data. ...
Page 188
... Adr D0_L 0 7 Adr-PAR Adr D0_L D1_L 7 BE_L 001 002 004 008 MegaCore function. pci_mt32 PCI Compiler Version 10.1 Figure 3–42, but the local D1_L D2_L Z Z BE_L D0-L-PAR D1-L-PAR D2-L-PAR D2_L 108 000 Altera Corporation January 2011 ...
Page 189
... Notes to Figure 3–40: (1) This signal is not applicable to the pci_mt32 MegaCore function. (2) For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions. Altera Corporation January 2011 shows the same transaction Adr D0_L 0 D0_H 0 ...
Page 190
... Also, because lm_lastn is asserted and lm_rdyn is deasserted in clock cycle 11, the lm_ackn and lm_dxfrn signals remain deasserted after clock cycle 12. 3–116 PCI Compiler User Guide shows the same transaction as in PCI Compiler Version 10.1 Figure 3–38 but with the PCI Altera Corporation January 2011 ...
Page 191
... For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions. Burst Memory Write Master Transactions with Variable Byte Enables Figure 3–42 variable byte enables. To allow this type of transaction, turn on Allow Variable Byte Enables During Burst Transactions on the Advanced PCI Altera Corporation January 2011 ...
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... Allow Variable Byte Enables During Burst Transactions turned on and the local side is providing unique byte enables for every data transfer. 3–118 PCI Compiler User Guide Figure 3–38 the local side provides byte enables at the Figure 3–42 the same transaction is shown with PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions. 32-Bit Single-Cycle Memory Write Master Transactions Figure 3–43 The transaction shown in Figure data word. This figure applies to both the pci_mt64 and pci_mt32 MegaCore functions, excluding the 64-bit extension signals as noted for pci_mt32. Altera Corporation January 2011 ...
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... Note to Figure 3–43: (1) This signal is not applicable to the pci_mt32 MegaCore function. 3–120 PCI Compiler User Guide Adr 0 7 Adr D0_L 7 BE_L 001 002 004 PCI Compiler Version 10 D0_L Z BE_L Z Adr-PAR D0-L-PAR 008 108 000 Altera Corporation January 2011 ...
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... Altera Corporation January 2011 The bit width of all devices is known, such embedded system All 64-bit master transactions are claimed by 64-bit targets that ...
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... PCI Compiler User Guide Adr D0_L Adr D0_H 7 BE_L BE_H 001 002 004 PCI Compiler Version 10 D0_L Z D0_H Z BE_L Z Z BE_H D0-L-PAR Adr-PAR D0-H-PAR 008 308 000 Altera Corporation January 2011 ...
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... Therefore, the pci_mt64 function registers l_adi[63..0] on the local side and transfers the lower 32-bit data word on l_adi[31..0] on the PCI side first, and the upper 32-bit data word on l_adi[63..32] afterwards. Altera Corporation January 2011 shows the same transaction as in PCI Compiler Version 10.1 ...
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... PCI Compiler User Guide Adr D0_L D0_H 0 7 BE_L Adr-PAR D0-L-PAR Adr D0_L D1_L D0_H D1_H 7 BE_L BE_H 002 004 008 Figure PCI Compiler Version 10 D1_L D1_H Z Z D0-H-PAR D1-L-PAR D1-H-PAR 108 000 3–43. This figure applies to Altera Corporation January 2011 ...
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... This process informs the local-side device that it has ended the transaction because the target issued a retry. 1 Altera Corporation January 2011 Latency timer expires Target retry Target disconnect without data ...
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... PCI status register bit 13. Therefore, the signal remains asserted until it is reset by the host. 3–126 PCI Compiler User Guide “Disconnect” on page “Disconnect” on page 3–79. When the pci_mt64 and 3–86. When the pci_mt64 and pci_mt32 PCI Compiler Version 10.1 3–79. When the Altera Corporation January 2011 ...