IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 154

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–24. Single Data Phase Disconnect in a Burst Write Transaction
Note to
(1)
3–80
PCI Compiler User Guide
This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
Figure
(1) l_dato[63..32]
(1) l_hdat_ackn
3–24:
(1) l_beno[7..4]
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
l_adro[31..0]
l_cmdo[3..0]
l_dato[31..0]
l_beno[3..0]
lt_tsr[11..0]
(1) req64n
(1) ack64n
cben[3..0]
lt_framen
(1) par64
ad[31..0]
devseln
lt_discn
lt_dxfrn
framen
lt_ackn
lt_rdyn
stopn
trdyn
irdyn
par
clk
1
Figure 3–24
transaction that ensures only a single data phase is completed.
Figure 3–24
extension signals as noted for pci_mt32 and pci_t32. In
1t_rdyn is asserted in clock cycle 5 and 1t_discn is asserted in clock
cycle 6. This transaction informs the PCI MegaCore function that the local
side is ready to accept data but also wants to disconnect. As a result, the
PCI MegaCore function disconnects after one data phase.
2
000
Adr
7
3
Adr-PAR
PCI Compiler Version 10.1
shows an example of a disconnect during a burst write
applies to all PCI MegaCore functions, excluding the 64-bit
4
BE0_H
BE0_L
D0_H
D0_L
5
381
D0-H-PAR
D0-L-PAR
6
Adr
7
BE0_L
BE0_H
7
D0_H
D0_L
781
BE1_H
BE1_L
D1_H
D1-L
8
D1-H_PAR
D1-L-PAR
9
381
10
Altera Corporation
000
11
Figure 3–24
January 2011