IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 170

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–96
PCI Compiler User Guide
1
2
3
5
6
Table 3–38. Zero-Wait State Burst Memory Read Master Transaction (Part 1 of 3)
Clock
Cycle
The local side asserts
The function outputs
function asserts
The PCI bus arbiter asserts
that the grant occurs immediately and the PCI bus is idle at the time
may not occur immediately in a real transaction. Before the function proceeds, it waits for
asserted and the PCI bus to be idle. A PCI bus idle state occurs when both
deasserted.
The function turns on its output drivers, getting ready to begin the address phase.
The function also asserts
and command for the transaction. During the same clock cycle, the local side must provide the PCI
address on
The function continues to assert its
asserts
The function begins the 64-bit memory read transaction with the address phase by asserting
framen
At the same time, the local side must provide the byte enables for the transaction on the
bus. The PCI MegaCore function uses this byte enable value throughout the transaction, and ignores
any changes to the signals on the
Enables During Burst Transactions option is turned on in the Parameterize - PCI Compiler
wizard, you must keep the byte enables constant throughout the rest of the transaction. Typically, the
byte enable values are set to 0x00 for master read transactions.
The local side also asserts
The function asserts
If the arbiter deasserts
lm_tsr[2]
arbiter deasserts
for more information.
lm_tsr[1]
and
l_adi[31..0]
in this clock cycle. For recommendations of how to accommodate scenarios where the
req64n
lm_tsr
gntn
Table 3–38
memory read master transaction. The 64-bit extension signals are not
applicable to the pci_mt32 function.
lm_tsr[2]
reqn
to indicate to the local side that the PCI bus has been granted.
.
lm_req64n
gntn
in less than three clock cycles, refer to
[0] to indicate to the local side that the master is requesting the PCI bus.
lm_adr_ackn
lm_rdyn
to the PCI bus arbiter to request bus ownership. At the same time, the
gntn
in less than 3 clock cycles, the PCI MegaCore function does not assert
PCI Compiler Version 10.1
and the PCI command on
shows the sequence of events for a 64-bit zero-wait state burst
to indicate to the local side that the PCI bus is in its address phase.
l_cbeni
to grant the PCI bus to the function. Although
reqn
to request a 64-bit transaction.
to indicate that it is ready to accept data.
signal until the end of the address phase. The function also
to indicate to the local side that it must provide the address
bus after this clock cycle. If the Allow Variable Byte
Event
l_cbeni[3..0]
“Design Consideration” on page 3–92
gntn
framen
is asserted, this action
.
Altera Corporation
Figure 3–31
and
January 2011
gntn
irdyn
l_cbeni
shows
to be
are