IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 340

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench Specifications
8–10
PCI Compiler User Guide
mem_wr_64
The mem_wr_64 command performs a memory write of the data to the
address provided in the command. This command can perform
single-cycle or burst 64-bit memory write depending on the value of the
qword argument.
■
■
Syntax:
Arguments:
This command performs a single-cycle 64-bit memory write if the
qword value is one.
This command performs a burst-cycle 64-bit memory write if the
qword value is greater than one. In a burst transaction, the first data
phase uses the data value provided in the command. The
subsequent data phases use values incremented sequentially by one
from the data provided in the command argument.
PCI Compiler Version 10.1
mem_wr_64(address, data, qword)
address
data
qword
Transaction address. This value must be in
hexadecimal radix.
Data used for first data phase. Subsequent
data phases use a value sequentially
incremented by one from this data. This value
must be in hexadecimal radix.
The number
A value of one indicates a single-cycle
memory write transaction. A value greater
than one indicates a burst transaction. This
value must be an integer.
QWORD
s written in a transaction.
Altera Corporation
January 2011