IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 94

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
3–20
PCI Compiler User Guide
lt_abortn
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Table 3–7. Target Signals Connecting to the Local Side (Part 1 of 3)
Name
Input
Input
Type
Target Local-Side Signals
Table 3–7
interface between the PCI MegaCore function and the local-side
peripheral device(s) during target transactions.
1
Low
Low
Polarity
When a local side transaction is not in progress, local side inputs
should be driven to the deasserted state.
summarizes the target interface signals that provide the
PCI Compiler Version 10.1
Local target abort request. The local side should assert this
signal requesting the PCI MegaCore function to issue a target
abort to the PCI master. The local side should request an abort
when it has encountered a fatal error and cannot complete the
current transaction.
Local target disconnect request. The
requests the PCI MegaCore function to issue a retry or a
disconnect. The PCI MegaCore function issues a retry or
disconnect depending on when the signal is asserted during a
transaction.
The PCI bus specification requires that a PCI target issues a
disconnect whenever the transaction exceeds its memory
space. When using PCI MegaCore functions, the local side is
responsible for asserting
its memory space.
lt_discn
Description
if the transaction crosses
lt_discn
Altera Corporation
January 2011
input