IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 98

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
3–24
PCI Compiler User Guide
lm_req32n
lm_req64n
lm_lastn
Table 3–9. PCI Master Signals Interfacing to the Local Side (Part 1 of 2)
Name
Input
Input
Input
Type
Master Local-Side Signals
Table 3–9
signals that provide the interface between the PCI MegaCore function
and the local-side peripheral device(s) during master transactions.
1
Polarity
Low
Low
Low
When a local side transaction is not in progress, local side inputs
should be deasserted.
summarizes the pci_mt64 and pci_mt32 master interface
PCI Compiler Version 10.1
Local master request 32-bit data transaction. The local side asserts
this signal to request ownership of the PCI bus for a 32-bit master
transaction. To request a master transaction, it is sufficient for the
local-side device to assert
requesting a 32-bit transaction, only
write transaction or
transaction is valid.
The local side cannot request the bus until the current master
transaction has completed. After being granted mastership of the
PCI bus, the
lm_tsr[3]
Local master request 64-bit data transaction. The local side asserts
this signal to request ownership of the PCI bus for a 64-bit master
transaction. To request a master transaction, it is sufficient for the
local side device to assert
requesting a 64-bit data transaction,
PCI transaction. When the target does not assert its
signal, the transaction will be 32 bits. In a 64-bit master write
transaction where the target does not assert its
pci_mt64
multiplexes the data appropriately to 32 bits on the PCI side. When
the local side requests 64-bit PCI transactions, it must ensure that
the address is at a
in
The local side cannot request the bus until the current master
transaction has completed. After being granted mastership of the
PCI bus, the
lm_tsr[3]
Local master last. This signal is driven by the local side to request
that the
current transaction. When the local side asserts this signal, the PCI
MegaCore function master interface deasserts
possible and asserts
begun. The local side must assert this signal for one clock cycle to
initiate the end of the current master transaction.
pci_mt32
pci_mt64
automatically accepts 64-bit data on the local side and
lm_req32n
lm_req64n
is deasserted.
is deasserted.
.
QWORD
l_dato[31..0]
or
irdyn
pci_mt32
boundary. This signal is not implemented
lm_req64n
lm_req32n
signal should be asserted only after
Description
signal should be asserted only after
to indicate that the last data phase has
master interface ends the
l_adi[31..0]
pci_mt64
for a master read
for one clock cycle. When
for one clock cycle. When
framen
Altera Corporation
ack64n
requests a 64-bit
ack64n
January 2011
for a master
as soon as
signal,