IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 261

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI
Configuration
Altera Corporation
January 2011
The third tab of the PCI Compiler wizard sets up the PCI Base Address
Registers (BARs) and the PCI Read-Only Registers.
PCI Base Address Registers
In the PCI Base Address Register box you define the number and type of
BARs as well as the system’s BAR address range. Up to six 32-bit BARs
can be defined. If you select 64 Bit PCI Bus in the PCI Data Bus Width
field (System Options - 2 tab), you have the option of defining one 64-bit
BAR and up to four 32-bit BARs. Refer to
Register Values” on page
You have the option to disable the I/O ordering between the
non-prefetchable master and prefetchable master BARs in Target Only
mode. If you turn on Disable IO Ordering between Non-Prefetchable
and Prefetchable BARs, the non-prefetchable master write/read is no
longer dependent on the prefetchable master write/read, resulting in low
latency non-prefetchable master write/read.
c
PCI Read-Only Registers
The values in the PCI Read-Only Registers box can all be edited in place.
When you change a value, the validity of the new value is automatically
checked. If the new value is out of range, the previous legal value is
substituted. For example, if you enter an illegal value such as 0xFFFF for
the Vendor ID, the value will be returned to its previous value. In
addition, a message is displayed that explains why the edit was ignored.
This message must be dismissed before you can proceed with other edits.
Setting the PCI Base Address Register Values
For transactions initiated on the PCI bus with a destination on the
Avalon-MM bus, the PCI bus address must be translated into an
Avalon-MM address. The PCI-Avalon bridge claims the PCI transaction
1
Disabling the I/O ordering between the non-prefetchable
master and prefetchable master BARs violates the PCI ordering
rules for bridge specification. It should therefore be used only in
embedded applications where designers can control the
ordering via the applications.
PCI Compiler Version 10.1
To implement a Host bridge device with no other PCI
master-capable devices, select the User-Defined Arbiter
Internal to Device option and connect the PCI gntn input
port to a physical 0. The bus will always be granted to the
Host Bridge.
6–11.
“Setting the PCI Base Address
Parameter Settings
6–11