IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 198

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
Figure 3–45. 32-Bit PCI & 64-Bit Local-Side Master Burst Memory Write Transaction
3–124
PCI Compiler User Guide
lm_adr_ackn
l_adi[63..32]
l_cbeni[3..0]
l_cbeni[7..4]
l_hdat_ackn
l_ldat_ackn
lm_tsr[9..0]
l_adi[31..0]
lm_req64n
cben[3..0]
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
devseln
lm_rdyn
ack64n
framen
req64n
stopn
trdyn
irdyn
reqn
gntn
par
clk
1
000
2
3
001
I/O & Configuration Write Master Transactions
I/O and configuration write transactions by definition are 32 bits wide.
The sequence of events is the same as in a 32-bit single-cycle memory
write master transaction, as shown in
both the pci_mt64 and pci_mt32 MegaCore functions, excluding the
64-bit extension signals as noted for pci_mt32.
4
5
PCI Compiler Version 10.1
Adr
002
0
0
7
6
BE_L
BE_H
D0_L
D0_H
004
Adr
7
7
Adr-PAR
D0_L
D1_H
D1_L
8
008
D0-L-PAR
9
BE_L
D0_H
Figure
10
D0-H-PAR
D1_L
3–43. This figure applies to
108
11
D1-L-PAR
D1_H
12
Altera Corporation
D1-H-PAR
13
January 2011
Z
Z
000
14