IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 182

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–108
PCI Compiler User Guide
Master Write Transactions
This section describes the behavior of the PCI MegaCore functions in the
following types of master write transactions:
■
■
Memory Write Transactions
The PCI MegaCore functions support the following types of matched bus
width and mismatched bus width memory write transactions in master
mode:
■
■
■
■
1
For each type of transaction, the following sequence of events is the same:
1.
2.
Memory write
I/O and configuration write
Burst memory write
32-bit single-cycle memory write
64-bit single-cycle memory write
Mismatched bus width memory write
The local side asserts lm_req32n (and lm_req64n in the case of a
64-bit transaction) to request a transaction. Consequently, the PCI
side asserts reqn to request mastership of the bus from the PCI
arbiter.
When the PCI bus arbiter grants mastership by asserting the gntn
signal, the local side asserts lm_adr_ackn to acknowledge the
transaction’s address and command. During the same clock cycle
when lm_adr_ackn is asserted, the local side provides the address
on the l_adi bus and the command on l_cbeni[3..0]. At the
same time, the pci_mt64 or pci_mt32 function turns on the
drivers for framen (and req64n, in the case of a 64-bit transaction.)
Mismatched bus-width transactions are 32-bit PCI transactions
performed by the pci_mt64 MegaCore function.
PCI Compiler Version 10.1
Altera Corporation
January 2011