IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 104

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–30
PCI Compiler User Guide
Note to
(1)
Address Offset
Table 3–13. Supported Configuration Registers Address Map
These registers are supported by the pci_mt64 and pci_mt32 MegaCore functions only.
0x00
0x02
0x04
0x06
0x08
0x09
0x0C
0x0D
0x0E
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x2E
0x30
0x34
0x3C
0x3D
0x3E
0x3F
Table
3–13:
0x00-0x01
0x02-0x03
0x04-0x05
0x06-0x07
0x08-0x08
0x09-0x0B
0x0C-0x0C
0x0D-0x0D
0x0E-0x0E
0x10-0x13
0x14-0x17
0x18-0x1B
0x1C-0x1F
0x20-0x23
0x24-0x27
0x28-0x2B
0x2C-0x2D
0x2E-0x2F
0x30-0x33
0x34-0x35
0x3C-0x3C
0x3D-0x3D
0x3E-0x3E
0x3F-0x3F
Reserved
Range
device ID register value on the Read-Only PCI Configuration Registers
page. The specified default state is defined as the state of the register
when the PCI bus is reset.
2/2
2/2
2/2
2/2
1/1
3/3
1/1
1/1
1/1
4/4
4/4
4/4
4/4
4/4
4/4
4/4
2/2
2/2
4/4
1/1
1/1
1/1
1/1
1/1
Bytes Used/
Reserved
PCI Compiler Version 10.1
Read
Read
Read/write
Read/write
Read
Read
Read/write
Read/write
Read
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read
Read
Read
Read/write
Read
Read/write
Read
Read
Read
Read/Write
ven_id
dev_id
comd
status
rev_id
class
cache
lat_tmr
header
bar0
bar1
bar2
bar3
bar4
bar5
cardbus_ptr
sub_ven_id
sub_id
exp_rom_bar
cap_ptr
int_ln
int_pin
min_gnt
max_lat
Mnemonic
Vendor ID
Device ID
Command
Status
Revision ID
Class code
Cache line size
Latency timer
Header type
Base address register
zero
Base address register one
Base address register two
Base address register
three
Base address register four
Base address register five
CardBus CIS pointer
Subsystem vendor ID
Subsystem ID
Expansion ROM BAR
Capabilities pointer
Interrupt line
Interrupt pin
Minimum grant
Maximum latency
Register Name
Altera Corporation
January 2011
(1)
(1)
(1)
(1)