IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 298

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Master Operation
7–30
PCI Compiler User Guide
Table 7–9. Translation of Avalon Requests to PCI Requests (Part 2 of 2)
Width
Data
Path
64
64
Avalon
Count
Burst
>1
>1
Read
Write
Operation
Type of
Figure 7–9
Avalon-to-PCI direction. There is an Avalon-MM slave port that provides
access to the PCI bus.
Any value
Any value
Avalon Byte Enables
PCI Compiler Version 10.1
shows the basic data paths and control structures in the
Attempt to do a 64 bit burst on PCI (
asserted). All data phases will have all PCI byte
enables asserted.
Note: If the target address space is only 32-bit
(ack64n not asserted) and the device disconnects
on an odd
resumed as a 32-bit burst (
Attempt to do a 64-bit burst on PCI (
asserted). All data phases will have PCI byte
enables identical to the Avalon byte enables.
Note: If the target address space is only 32-bit
(ack64n not asserted) and the device disconnects
on an odd
asserted), a single cycle 32-bit write operation will
be issued to get back on an even
boundary. This is followed by an attempt at a 64-bit
burst that is converted to a 32-bit burst if the device
doesn’t acknowledge 64-bit bursts.
Resulting PCI Operation and Byte Enables
DWORD
DWORD
boundary, the transaction is
boundary (
req64n
req64n
Altera Corporation
DWORD
not asserted).
req64n
req64n
January 2011
not