IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 177

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Single-Cycle Memory Read Master Transaction
Figure 3–35
Figure 3–35
data phase. This figure applies to both the pci_mt64 and pci_mt32
MegaCore functions, excluding the 64-bit extension signals as noted for
pci_mt32. In clock cycle 6, framen and req64n are asserted to begin
the address phase. At the same time, the local side should assert the
lm_lastn signal on the local side to indicate that it wants to transfer only
one 64-bit data word. In a real application, in order to indicate a single-
cycle 64-bit data transfer, the lm_lastn signal can be asserted on any
clock cycle between the assertion of lm_req64n and the address phase.
1
If your application is a system that has only 64-bit PCI devices
and the local side wants to transfer one 64-bit data word, Altera
recommends that you perform a 64-bit single-cycle memory
read master transaction. However, if your application is a
system that has 32-bit and 64-bit PCI devices and the local side
wants to transfer one 64-bit data word, Altera recommends that
you perform a 32-bit burst memory read transaction.
PCI Compiler Version 10.1
shows a 64-bit single-cycle memory read master transaction.
shows the same transaction as in
Figure 3–31
Functional Description
with just one
3–103