IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 216

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench Specifications
Testbench
Specifications
4–6
PCI Compiler User Guide
Interrupt acknowledge cycle
I/O read
I/O write
Memory read
Memory write
Configuration read
Configuration write
Memory read multiple
Memory write multiple
Dual address cycle
Memory read line
Memory write and invalidate
Table 4–4. PCI Testbench PCI Bus Transaction Support
Transactions
This section describes the modules used by the PCI testbench including
master commands, setting and controlling target termination responses,
bus parking, and PCI bus speed settings. Refer to
diagram of the PCI testbench. The Altera PCI testbench has the following
modules:
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The PCI testbench consists of VHDL and Verilog HDL. If your application
requires a feature that is not supported by the PCI testbench, you can
modify the source code to add the feature. You can also modify the
existing behavior to fit your application needs.
Table 4–4
Master Transactor Target Transactor
Master transactor (mstr_tranx)
Target transactor (trgt_tranx)
Bus monitor (monitor)
Clock generator (clk_gen)
Arbiter (arbiter)
Pull ups (pull_ups)
A local reference design
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shows the PCI bus transactions supported by the PCI testbench.
PCI Compiler Version 10.1
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Local Master
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Figure 4–1
Altera Corporation
Local Target
January 2011
for a block
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