IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 64

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Advanced PCI MegaCore Function Features
2–6
PCI Compiler User Guide
Disable Master Latency Timer
Turning on the Disable Master Latency Timer option allows you to
disable the latency timer time-out feature. If the latency timer time-out is
disabled, the master will continue the burst transaction even if the latency
timer has expired and the gntn signal is removed. This feature is useful
in systems in which breaking up long data transfers in small transactions
will yield undesirable side effects.
1
Assume ack64n Response
This feature provides enhanced master functionality when using the
pci_mt64 MegaCore function in systems where a 64-bit transaction
request is always accepted by a 64-bit target asserting ack64n. This
feature can be used where the bit width of all devices is known, such as
in an embedded system, and where all 64-bit targets respond with
ack64n asserted.
With this option turned on, the pci_mt64 master supports 64-bit single-
cycle write transactions and asserts irdyn one clock cycle after framen
is asserted. For more information, refer to
Write Master Transactions” on page
Disabling the Disable Master Latency Timer violates the PCI
specification and therefore should only be used in embedded
applications where the designer can control the entire system
configuration. Disabling the master latency timer can also result
in increased latency for other master devices in the system. If
increased latency for other master devices is unacceptable in
your application, this option should not be used.
PCI Compiler Version 10.1
3–121.
“64-Bit Single Cycle Memory
Altera Corporation
January 2011