IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 346

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulation Flow
8–16
PCI Compiler User Guide
3.
4.
5.
Refer to
model instantiated in the PCI testbench.
The master transactor defines the procedures (VHDL) or tasks
(Verilog HDL) needed to initiate PCI transactions in your testbench.
Add the commands that correspond to the transactions you want to
implement in your tests to the master transactor model source code.
At a minimum, you must add configuration commands to set the
BAR for the target transactor model and write the configuration
space of the PCI MegaCore function. Additionally, you can add
commands to initiate memory or I/O transactions to the PCI
MegaCore function.
Refer to
commands.
Compile the files in your simulator, including the testbench
modules and the files created by SOPC Builder.
Simulate the testbench for the desired time period.
PCI Compiler Version 10.1
Figure 8–1
Table 8–4 on page 8–7
for a block diagram of the Master Transactor
for more information about the user
Altera Corporation
January 2011