IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 130

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–10. Burst Memory Read Target Transaction with Local-Side Wait State
Note to
(1)
3–56
PCI Compiler User Guide
(1) l_adi[63..32]
(1) ad[63..32]
(1) cben[7..4]
l_adro[31..0]
l_cmdo[3..0]
lt_tsr[11..0]
l_adi[31..0]
(1) req64n
(1) ack64n
cben[3..0]
lt_framen
(1) par64
ad[31..0]
This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
devseln
lt_dxfrn
lt_ackn
framen
lt_rdyn
stopn
trdyn
irdyn
par
Figure
clk
1
3–10:
2
000
Adr
6
3
Figure 3–10
local side inserting a wait state. The local side deasserts lt_rdyn in clock
cycle 6. Deasserting lt_rdyn in clock cycle 6 suspends the local side data
transfer in clock cycle 7 by deasserting the lt_dxfrn signal. Because no
data is transferred in clock cycle 7 from the local side, the PCI MegaCore
function deasserts trdyn in clock cycle 8 thus inserting a PCI wait state.
Adr-PAR
4
Z
Z
PCI Compiler Version 10.1
Z
shows the same transaction as shown in
5
BE0_H
BE0_H
BE0_L
381
6
D0_H
D0_L
7
D0_H
D0_L
8
D0-H-PAR
D0-L-PAR
D1_H
D1_L
Adr
781
6
BE1_L
BE1_H
9
D1_H
D2_H
D1_L
D2_L
381
10
D1-H-PAR
D1-L-PAR
BE2_L
BE2_H
D2_H
D3_H
D2_L
D3_L
Figure 3–8
Altera Corporation
11
781
D2-H-PAR
D2-L-PAR
January 2011
12
with the
Z
Z
000
13