IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 28

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Performance and Resource Utilization
16
PCI Compiler User Guide
Notes to
(1)
(2)
(3)
Notes to
(1)
(2)
PCI
Master/
Target
PCI
Target-Only
Table 10. Memory Utilization & Performance Data for Stratix, Stratix GX & Cyclone Devices
of 2)
Table 11. Memory Utilization & Performance Data for MAX II Devices
Device
Mode
Device
Mode
PCI
Min = Single-cycle transactions
Typical = Burst transactions with a single pending read
Max = Burst transactions with multiple pending reads
In Cyclone devices, memory is implemented in M4K blocks, not M512 blocks.
The data was obtained by performing compilations on a Cyclone EP1C20F400C7 device. Each of the device types
was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI
Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side.
Min = Single-cycle transactions
The data was obtained by performing compilations on a MAX II EPM2210F324C3 device. The device type was
parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side.
PCI
Table
Table
Performance Setting as:
Min
Typical
Max
Min
Typical
Max
PCI Target
10:
11:
Min
Performance Setting as:
PCI Target
Typical
Typical
Typical
Max
Max
Max
PCI Master
Table 11
devices.
1
N/A
PCI Master
(1)
lists memory utilization and performance data for MAX II
MAX II devices only support the PCI Target-Only peripheral
and the single-cycle performance setting.
PCI Compiler Version 10.1
(1)
Elements
Logic
2,715
3,053
3,540
3,728
4,059
4,788
(LEs)
32-Bit PCI Interface
Elements
Logic
(LEs)
Memory
770
Blocks
M512
(2)
10
12
14
7
9
9
32-Bit PCI Interface
Pins
I/O
50
50
50
50
50
50
Memory
Blocks
0
Elements
(2)
Logic
3,668
4,187
4,682
5,138
5,634
6,696
(LEs)
64-Bit PCI Interface
I/O Pins
Memory
Blocks
M512
48
(2)
10
14
14
16
20
22
Altera Corporation
Pins
I/O
89
89
89
89
89
89
January 2011
(3)
PCI f
(MHz)
>67
(Part 2
(MHz)
MAX
f
>67
>67
>67
>67
>67
>67
PCI
MAX