IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 336
IPR-PCI/MT32
Manufacturer Part Number
IPR-PCI/MT32
Description
IP CORE Renewal Of IP-PCI/MT32
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT32
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 336 of 358
- Download datasheet (3Mb)
Testbench Specifications
8–6
PCI Compiler User Guide
The master transactor terminates the PCI transactions in the following
cases:
■
■
■
The bus monitor informs the master transactor of a successful data
transaction or a target termination. Refer to the source code, which shows
you how the master transactor uses these termination signals from the
bus monitor.
The PCI testbench master transactor PROCEDURES and TASKS sections
implement basic PCI transaction functionality. If your application
requires different functionality, modify the events to change the behavior
of the master transactor. Additionally, you can create new procedures or
tasks in the master transactor by using the existing events as an example.
INITIALIZATION Section
This user-defined section defines the parameters and reset length of your
PCI bus on power-up. Specifically, the system should reset the bus and
write the configuration space of the PCI agents. You can modify the
master transactor INITIALIZATION section to match your system
requirements by changing the time that the system reset is asserted and
by modifying the data written in the configuration space of the PCI
agents.
The PCI transaction has successfully transferred all the intended
data.
The PCI target terminates the transaction prematurely with a target
retry, disconnect, or abort as defined in the PCI Local Bus Specification,
Revision 3.0.
A target does not claim the transaction resulting in a master abort.
PCI Compiler Version 10.1
Altera Corporation
January 2011
Related parts for IPR-PCI/MT32
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/4
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet: