IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 327

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
2:0
3
4
5
6
31:7
Table 7–27. Current PCI Status Register – Address 0x306C
Bit
Reserved
MASTER_ENABLE_CURRENT_VALUE
Reserved
A2P_WRITE_IN_PROGRESS
INTAN_CURRENT_VALUE
Reserved
Name
Table 7–27
the current status of the PCI rstn and int[a:d]n lines.
PCI Compiler Version 10.1
describes the current PCI status register. This register shows
N/A
RO
N/A
RO
RO
N/A
Access
Mode
Current value of the PCI command register
master enable bit (command register bit 2).
0 – Not enabled to master transactions on the PCI
bus.
1 – Enabled to master transactions on the PCI
bus.
This bit will always be set to 0 when the bridge is
operating in the PCI target mode.
0 – There are no Avalon-to-PCI writes pending in
the PCI-Avalon bridge module
1 – There is at least one Avalon-to-PCI write
pending in the PCI-Avalon bridge module
Due to clock synchronization delays, there will be
a slight delay between an Avalon-to-PCI write
entering the bridge module and this bit being set.
The delay could be up to five of the slowest clock
cycles.
If an application is concerned about the
completion of configuration writes on the target
bus, the configuration write can be issued by itself
and then this bit can be read to confirm when the
write is no longer pending. The
ERR_PCI_WRITE_FAILURE
checked to determine if there was an error on the
write.
Current value of the PCI
0 – PCI int A is being signaled.
1 – PCI int A is not being signaled.
This bit is only implemented when the bridge is
operating in the PCI Host-Bridge Device mode.
Description
intan
Functional Description
bit should be
signal.
7–59