IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 187

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
9
10
11
12
13
Table 3–39. Zero-Wait State Burst Memory Write Master Transaction (Part 3 of 3)
Clock
Cycle
Because
on the rising edge of clock cycle 10.
The function asserts
Because
cycle, the function asserts
l_hdat_ackn
l_adi
The function asserts
was completed successfully on the PCI bus during the previous clock cycle. The function also asserts
lm_tsr[9]
ack64n
Because
the rising edge of clock 11.
The function asserts
Because
cycle, the function asserts
l_hdat_ackn
l_adi
expected on the
10 is the last data phase on the local side.
The function also asserts
successful data transfer has occurred on the PCI bus during the previous clock cycle.
Because
function deasserts
trdyn
12.
On the local side, the function deasserts
local side was completed on the previous cycle.
The function continues to assert
has occurred on the PCI bus during the previous clock cycle.
The function deasserts
devseln
will be no additional data phases.
The function continues to assert
has occurred on the PCI bus during the previous clock cycle.
The function deasserts
completed.
is asserted, the last data phase is completed on the PCI side on the rising edge of clock cycle
bus.
bus. Also, the assertion of the
.
irdyn
lm_rdyn
irdyn
lm_rdyn
lm_lastn
,
ack64n
to inform the local side that the PCI target has claimed the 64-bit transaction with
signals indicates to the local side that it has transferred one data word from the
signals indicates to the local side that it has transferred one data word from the
l_adi
and
and
framen
, and
was asserted in the previous cycle and
was asserted in the previous cycle and
lm_tsr[8]
lm_ackn
lm_ackn
trdyn
trdyn
was asserted and a data phase was completed in the previous cycle, the
irdyn
lm_tsr[3]
bus. Also, the assertion of the
trdyn
lm_tsr[8]
lm_dxfrn
lm_dxfrn
and
are asserted, the second 64-bit data word is transferred to the PCI side
are asserted, the third 64-bit data word is transferred to the PCI side on
PCI Compiler Version 10.1
and tri-states
to inform the local side that the PCI side is ready to accept data.
to inform the local side that the PCI side is ready to accept data.
lm_tsr[8]
lm_tsr[8]
req64n
. These actions indicate that the transaction has ended and there
in the same clock cycle to inform the local side that a data phase
, informing the local side that the data transfer mode is
lm_lastn
. The assertion of the
. The assertion of the
in the same clock cycle to inform the local side that a
lm_ackn
and asserts
, informing the local side that a successful data transfer
, informing the local side that a successful data transfer
framen
Event
signal indicates to the local side that valid data is
and
irdyn
and
lm_lastn
lm_dxfrn
req64n
lm_ackn
lm_ackn
lm_dxfrn
lm_dxfrn
to signal the last data phase. Because
signal indicates that clock cycle
since the last data phase on the
. The PCI target deasserts
is asserted in the current
is asserted in the current
,
,
l_ldat_ackn
l_ldat_ackn
Functional Description
, and
, and
3–113