IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 16

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Features
4
PCI Compiler User Guide
■
■
■
■
PCI Compiler with MegaWizard Plug-in Manager Flow
The following list outlines the features of the PCI Compiler with
MegaWizard Plug-in Manager flow.
■
■
■
■
PCI Compiler with SOPC Builder Flow
The following list outlines the features of the PCI Compiler with SOPC
Builder flow.
■
■
IP functional simulation models enable simulation of a register
transfer level (RTL) model of a PCI MegaCore function in VHDL and
Verilog HDL simulators
OpenCore Plus hardware evaluation feature enables testing of a
PCI MegaCore function in hardware prior to purchasing a license
Configuration registers:
●
●
●
Host bridge application support
IP Toolbench wizard-driven interface makes it easy to generate a
custom variation of a PCI MegaCore function
PCI target features:
●
●
●
●
PCI master features (pci_mt64 and pci_mt32 only):
●
●
64-bit PCI features (pci_mt64 and pci_t64 only):
●
●
●
●
SOPC Builder ready
PCI complexities, such as retry and disconnect are handled by the
PCI/Avalon Bridge logic and transparent to the user
Parameterized registers: device ID, vendor ID, class code,
revision ID, BAR0 through BAR5, subsystem ID, subsystem-
vendor ID, maximum latency, minimum grant, capabilities list
pointer, expansion ROM BAR
Parameterized default or preset base address (available for all
six BARs) and expansion ROM base address
Non-parameterized registers: command, status, header type 0,
latency timer, cache line size, interrupt pin, interrupt line
Capabilities list pointer support
Expansion ROM BAR support
Local-side requests for target abort, retry, or disconnect
Local-side interrupt requests
Allows on-chip arbitration logic
Allows disabling latency timer
64-bit addressing support as both master and target
Initiates 64-bit addressing, using dual-address cycle (DAC)
Initiates 64-bit memory transactions
Dynamically negotiates 64-bit transactions and automatically
multiplexes data on the local 64-bit data bus
PCI Compiler Version 10.1
Altera Corporation
January 2011