IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 162

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
Master Mode
Operation
3–88
PCI Compiler User Guide
Additional Design Guidelines for Target Transactions
Altera recommends that the local-side application deassert the lt_rdyn
signal after the target transaction completes to avoid false triggering of
internal state machines if the next target transaction begins immediately.
You can detect that the current target transaction has completed if
lt_ackn and lt_tsr[8] are both deasserted.
Asserting wait states on the last data phase of a PCI write transaction can
cause a data loss if another PCI transaction begins during the wait states.
This is because the PCI MegaCore function has only one register pipeline
phase that is used to register the PCI data. To prevent data loss, the local
side design should load the data into a holding register if a wait state is
needed on the last data phase.
The local-side design must ensure that PCI latency rules are not violated
while the PCI MegaCore function waits to transfer data. If the local-side
design is unable to meet the latency requirements, it must assert
lt_discn to request that the PCI MegaCore function terminate the
transaction. The PCI target latency rules state that the time to complete
the first data phase must not be greater than 16 clock cycles, and the
subsequent data phases must not take more than 8 clock cycles to
complete.
The PCI Local Bus Specification, Revision 3.0 requires that a target device
issues a disconnect if a burst transaction goes beyond its address range.
In this case, the local-side device must request a disconnect. The local-side
device must keep track of the current data transfer address; if the transfer
exceeds its address range, the local side should request a disconnect by
asserting lt_discn.
The PCI Local Bus Specification, Revision 3.0 requires that a target device
issues an abort if the target device shares bytes in the same DWORD with
another device, and the byte enable combination received byte requests
outside its address range. This condition most commonly occurs during
I/O transactions. The local-side device must ensure that this requirement
is met, and if it receives this type of transaction, it must assert lt_abortn
to request a target abort termination.
This section describes all supported master transactions for both the
pci_mt64 and pci_mt32 functions. Although this section includes
waveform diagrams showing typical PCI cycles in master mode for the
PCI Compiler Version 10.1
Altera Corporation
January 2011