IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 129

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–23. Completion Signals for the Avalon-ST Interface (Part 1 of 2)
December 2010 Altera Corporation
cpl_err[6:0]
Signal
f
For a description of the completion rules, the completion header format, and
completion status field values, refer to Section 2.2.9 of the
Specification, Rev.
I/O
I
I
Completion error. This signal reports completion errors to the configuration
space. When an error occurs, the appropriate signal is asserted for one cycle.
■
■
■
■
■
■
2.0.
cpl_err[0]: Completion timeout error with recovery. This signal should be
asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
timeout period when the error is correctable. The IP core automatically
generates an advisory error message that is sent to the root complex.
cpl_err[1]: Completion timeout error without recovery. This signal should
be asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
time-out period when the error is not correctable. The IP core automatically
generates a non-advisory error message that is sent to the root complex.
cpl_err[2]:Completer abort error. The application asserts this signal to
respond to a posted or non-posted request with a completer abort (CA)
completion. In the case of a non-posted request, the application generates and
sends a completion packet with completer abort (CA) status to the requestor
and then asserts this error signal to the IP core. The IP core automatically sets
the error status bits in the configuration space register and sends error
messages in accordance with the
cpl_err[3]:Unexpected completion error. This signal must be asserted when
an application layer master block detects an unexpected completion
transaction. Many cases of unexpected completions are detected and reported
internally by the transaction layer of the IP core. For a list of these cases, refer
to
cpl_err[4]: Unsupported request error for posted TLP. The application
asserts this signal to treat a posted request as an unsupported request (UR).
The IP core automatically sets the error status bits in the configuration space
register and sends error messages in accordance with the
Specification
internally by the transaction layer of the IP core. For a list of these cases, refer
to
cpl_err[5]: Unsupported request error for non-posted TLP. The application
asserts this signal to respond to a non-posted request with an unsupported
request (UR) completion. In this case, the application sends a completion
packet with the unsupported request status back to the requestor, and asserts
this error signal to the IP core. The MegaCore automatically sets the error
status bits in the configuration space register and sends error messages in
accordance with the
unsupported requests are detected and reported internally by the transaction
layer of the IP core. For a list of these cases, refer to
Transaction Layer” on page
“Errors Detected by the Transaction Layer” on page
“Errors Detected by the Transaction Layer” on page
. Many cases of unsupported requests are detected and reported
PCI Express Base Specification
12–3.
Description
PCI Express Base Specification
PCI Express Base
PCI Express Compiler User Guide
“Errors Detected by the
. Many cases of
12–3.
12–3.
PCI Express Base
.
5–45