IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 205

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 12: Error Handling
Error Reporting and Data Poisoning
Table 12–4. Errors Detected by the Transaction Layer (Part 3 of 3)
Error Reporting and Data Poisoning
December 2010 Altera Corporation
Malformed TLP
Malformed TLP
(continued)
Note to
(1) Considered optional by the
Table
Error
12–4:
f
How the endpoint handles a particular error depends on the configuration registers of
the device.
Refer to the
signaling and logging for an endpoint.
The IP core implements data poisoning, a mechanism for indicating that the data
associated with a transaction is corrupted. Poisoned transaction layer packets have
the error/poisoned bit of the header set to 1 and observe the following rules:
■
■
■
Received poisoned transaction layer packets are sent to the application layer and
status bits are automatically updated in the configuration space. In PCI Express
1.1, this is treated as an advisory error.
Received poisoned configuration write transaction layer packets are not written in
the configuration space.
The configuration space never generates a poisoned transaction layer packet; the
error/poisoned bit of the header is always set to 0.
PCI Express Base Specification Revision 1.0a, 1.1 or
Uncorrectable
(fatal)
Uncorrectable
(fatal)
Type
PCI Express Base Specification 1.0a, 1.1 or 2.0
This error is caused by any of the following conditions:
■
■
■
■
■
■
■
■
The IP core deletes the malformed TLP; it is not presented to the
application layer.
The data payload of a received transaction layer packet exceeds the
maximum payload size.
The TD field is asserted but no transaction layer packet digest exists,
or a transaction layer packet digest exists but the TD bit of the PCI
Express request header packet is not asserted.
A transaction layer packet violates a byte enable rule. The IP core
checks for this violation, which is considered optional by the PCI
Express specifications.
A transaction layer packet in which the type and length fields do not
correspond with the total length of the transaction layer packet.
A transaction layer packet in which the combination of format and
type is not specified by the PCI Express specification.
A request specifies an address/length combination that causes a
memory space access to exceed a 4 KByte boundary. The IP core
checks for this violation, which is considered optional by the PCI
Express specification.
Messages, such as Assert_INTX, power management, error
signaling, unlock, and Set_Slot_power_limit, must be transmitted
across the default traffic class.
A transaction layer packet that uses an uninitialized virtual channel.
2.0.
Description
for a description of the device
PCI Express Compiler User Guide
12–5