IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 80

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–22
PCI Express Compiler User Guide
The address translation table contains up to 512 possible address translation entries
that you can configure. Each entry corresponds to a base address of the PCI Express
memory segment of a specific size. The segment size of each entry must be identical.
The total size of all the memory segments is used to determine the number of address
MSB bits to be replaced. In addition, each entry has a 2-bit field, Sp[1:0], that
specifies 32-bit or 64-bit PCI Express addressing for the translated address. Refer to
Figure 4–12 on page
used by the system interconnect fabric to select the slave port and are not available to
the slave. The next most significant bits of the Avalon-MM address index the address
translation entry to be used for the translation process of MSB replacement.
For example, if the core is configured with an address translation table with the
following attributes:
■
■
■
then the values in
■
■
■
■
In this case, the Avalon address is interpreted as follows:
■
■
■
■
The address translation table can be hardwired or dynamically configured at run
time. When the IP core is parameterized for dynamic address translation, the address
translation table is implemented in memory and can be accessed through the CRA
slave module. This access mode is useful in a typical PCI Express system where
address allocation occurs after BIOS initialization.
For more information about how to access the dynamic address translation table
through the control register access slave, refer to the
Address Translation Table” on page
Number of Address Pages—16
Size of Address Pages—1 MByte
PCI Express Address Size—64 bits
N = 20 (due to the 1 MByte page size)
Q = 16 (number of pages)
M = 24 (20 + 4 bit page selection)
P = 64
Bits [31:24] select the TX slave module port from among other slaves connected to
the same master by the system interconnect fabric. The decode is based on the base
addresses assigned in SOPC Builder.
Bits [23:20] select the address translation table entry.
Bits [63:20] of the address translation table entry become PCI Express address bits
[63:20].
Bits [19:0] are passed through and become PCI Express address bits [19:0].
Figure 4–12
4–23. The most significant bits of the Avalon-MM address are
are:
6–9.
“Avalon-MM-to-PCI Express
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge