IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 162

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–2
Figure 7–1. Reset Modules in the Hard IP Implementation
Note to
(1) Refer to
PCI Express Compiler User Guide
Figure
<variant>_example_chaining_pipen1b.v or .vhd
pcie_rstn
local_rstn
Figure 7–2
7–1:
PCI Express Plus Hard IP Core
<variant>_plus.v or .vhd
f
1
<variant>_rs_hip.v
for more detail on this variant.
pld_clk 125 MHz
Transceiver Reset
free_running_clock 100 MHz
■
■
■
Figure 7–1
<variant>.v or .vhd options.
coreclk_out 125 MHz
Refer to “PCI Express (PIPE) Reset Sequence” in the
chapter in volume of volume 2 of the Stratix IV Device Handbook for a timing diagram
illustrating the reset sequence.
To understand the reset sequence in detail, you can also review altpcie_rs_serdes.v
file.
app_rstn
or .vhd
Reset circuitry
ALTGXB Reconfiguration IP core
Test_in settings
dl_up, hotrst_exit,
l2_exit, ltssm
illustrates the reset logic for both the <variant>_plus.v or .vhd and
crst
srst
<variant>.v or .vhd
<variant>_core.v
PCI Express
Hard IP
or .vhd
busy_altgxb_reconfig
altpcierd_reconfig_pll_clk.v
Note (1)
Hip_txclk 125 or 250 MHz
PLL
altpcie_rs_serdes.v
<device>.v or .vhd
ALTGXB_Reconfig
altpcie_reconfig_
Transceiver Reset
locked
or .vhd
Reset Control and Power Down
reconfig_clk
fixedclk
December 2010 Altera Corporation
<variant>_serdes.v
PHY IP Core
Chapter 7: Reset and Clocks
Reset Hard IP Implementation
Transceiver
50 MHz
125 MHz
or .vhd
cal_blk_clk
50 MHz
100 MHz
Refclk